\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :
IMR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCSTAMPTAMPLSECSSIM : RTCSTAMPTAMPLSECSSIM
bits : 0 - 0 (1 bit)
RTCSSRUIM : RTCSSRUIM
bits : 2 - 2 (1 bit)
EXTI5IM : Peripheral EXTI5 interrupt mask to CPU1
bits : 21 - 21 (1 bit)
EXTI6IM : Peripheral EXTI6 interrupt mask to CPU1
bits : 22 - 22 (1 bit)
EXTI7IM : Peripheral EXTI7 interrupt mask to CPU1
bits : 23 - 23 (1 bit)
EXTI8IM : Peripheral EXTI8 interrupt mask to CPU1
bits : 24 - 24 (1 bit)
EXTI9IM : Peripheral EXTI9 interrupt mask to CPU1
bits : 25 - 25 (1 bit)
EXTI10IM : Peripheral EXTI10 interrupt mask to CPU1
bits : 26 - 26 (1 bit)
EXTI11IM : Peripheral EXTI11 interrupt mask to CPU1
bits : 27 - 27 (1 bit)
EXTI12IM : Peripheral EXTI12 interrupt mask to CPU1
bits : 28 - 28 (1 bit)
EXTI13IM : Peripheral EXTI13 interrupt mask to CPU1
bits : 29 - 29 (1 bit)
EXTI14IM : Peripheral EXTI14 interrupt mask to CPU1
bits : 30 - 30 (1 bit)
EXTI15IM : Peripheral EXTI15 interrupt mask to CPU1
bits : 31 - 31 (1 bit)
IMR2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PVM3IM : Peripheral xxx interrupt mask to CPU1
bits : 18 - 18 (1 bit)
PVDIM : Peripheral xxx interrupt mask to CPU1
bits : 20 - 20 (1 bit)
C2IMR1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCSTAMPTAMPLSECSSIM : Peripheral RTCSTAMPTAMPLSECSS interrupt mask to CPU2
bits : 0 - 0 (1 bit)
RTCALARMIM : Peripheral RTCALARM interrupt mask to CPU2
bits : 1 - 1 (1 bit)
RTCSSRUIM : RTCSSRUIM
bits : 2 - 2 (1 bit)
RTCWKUPIM : Peripheral RTCWKUP interrupt mask to CPU2
bits : 3 - 3 (1 bit)
RCCIM : Peripheral RCC interrupt mask to CPU2
bits : 5 - 5 (1 bit)
FLASHIM : Peripheral FLASH interrupt mask to CPU2
bits : 6 - 6 (1 bit)
PKAIM : PKAIM
bits : 8 - 8 (1 bit)
AES1IM : AES1IM
bits : 10 - 10 (1 bit)
COMPIM : Peripheral COMP interrupt mask to CPU2
bits : 11 - 11 (1 bit)
ADCIM : Peripheral ADC interrupt mask to CPU2
bits : 12 - 12 (1 bit)
DAC1IM : Peripheral DAC1 interrupt mask to CPU2
bits : 13 - 13 (1 bit)
EXTI0IM : Peripheral EXTI0 interrupt mask to CPU2
bits : 16 - 16 (1 bit)
EXTI1IM : Peripheral EXTI1 interrupt mask to CPU2
bits : 17 - 17 (1 bit)
EXTI2IM : Peripheral EXTI2 interrupt mask to CPU2
bits : 18 - 18 (1 bit)
EXTI3IM : Peripheral EXTI3 interrupt mask to CPU2
bits : 19 - 19 (1 bit)
EXTI4IM : Peripheral EXTI4 interrupt mask to CPU2
bits : 20 - 20 (1 bit)
EXTI5IM : Peripheral EXTI5 interrupt mask to CPU2
bits : 21 - 21 (1 bit)
EXTI6IM : Peripheral EXTI6 interrupt mask to CPU2
bits : 22 - 22 (1 bit)
EXTI7IM : Peripheral EXTI7 interrupt mask to CPU2
bits : 23 - 23 (1 bit)
EXTI8IM : Peripheral EXTI8 interrupt mask to CPU2
bits : 24 - 24 (1 bit)
EXTI9IM : Peripheral EXTI9 interrupt mask to CPU2
bits : 25 - 25 (1 bit)
EXTI10IM : Peripheral EXTI10 interrupt mask to CPU2
bits : 26 - 26 (1 bit)
EXTI11IM : Peripheral EXTI11 interrupt mask to CPU2
bits : 27 - 27 (1 bit)
EXTI12IM : Peripheral EXTI12 interrupt mask to CPU2
bits : 28 - 28 (1 bit)
EXTI13IM : Peripheral EXTI13 interrupt mask to CPU2
bits : 29 - 29 (1 bit)
EXTI14IM : Peripheral EXTI14 interrupt mask to CPU2
bits : 30 - 30 (1 bit)
EXTI15IM : Peripheral EXTI15 interrupt mask to CPU2
bits : 31 - 31 (1 bit)
C2IMR2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1CH1IM : Peripheral DMA1CH1 interrupt mask to CPU2
bits : 0 - 0 (1 bit)
DMA1CH2IM : Peripheral DMA1CH2 interrupt mask to CPU2
bits : 1 - 1 (1 bit)
DMA1CH3IM : Peripheral DMA1CH3 interrupt mask to CPU2
bits : 2 - 2 (1 bit)
DMA1CH4IM : Peripheral DMA1CH4 interrupt mask to CPU2
bits : 3 - 3 (1 bit)
DMA1CH5IM : Peripheral DMA1CH5 interrupt mask to CPU2
bits : 4 - 4 (1 bit)
DMA1CH6IM : Peripheral DMA1CH6 interrupt mask to CPU2
bits : 5 - 5 (1 bit)
DMA1CH7IM : Peripheral DMA1CH7 interrupt mask to CPU2
bits : 6 - 6 (1 bit)
DMA2CH1IM : Peripheral DMA2CH1 interrupt mask to CPU2
bits : 8 - 8 (1 bit)
DMA2CH2IM : Peripheral DMA2CH2 interrupt mask to CPU2
bits : 9 - 9 (1 bit)
DMA2CH3IM : Peripheral DMA2CH3 interrupt mask to CPU2
bits : 10 - 10 (1 bit)
DMA2CH4IM : Peripheral DMA2CH4 interrupt mask to CPU2
bits : 11 - 11 (1 bit)
DMA2CH5IM : Peripheral DMA2CH5 interrupt mask to CPU2
bits : 12 - 12 (1 bit)
DMA2CH6IM : Peripheral DMA2CH6 interrupt mask to CPU2
bits : 13 - 13 (1 bit)
DMA2CH7IM : Peripheral DMA2CH7 interrupt mask to CPU2
bits : 14 - 14 (1 bit)
DMAMUX1IM : Peripheral DMAMUX1 interrupt mask to CPU2
bits : 15 - 15 (1 bit)
PVM3IM : Peripheral PVM3 interrupt mask to CPU2
bits : 18 - 18 (1 bit)
PVDIM : Peripheral PVD interrupt mask to CPU2
bits : 20 - 20 (1 bit)
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