VERSION_ID

PGA_CONF

SWITCH

DF_CONF

DS_CONF

SEQ_1

SEQ_2

COMP_1

COMP_2

COMP_3

COMP_4

COMP_SEL

WD_TH

CONF

WD_CONF

DS_DATAOUT

DF_DATAOUT

IRQ_STATUS

IRQ_ENABLE

TIMER_CONF

TEST_CONF

DTB_CONF

CTRL

OCM_CTRL

VERSION_ID : version of the embedded IP.
bits : 0 - 7 (8 bit)

PGA_GAIN : from 6 to 30 dB
bits : 0 - 3 (4 bit)

PGA_BIAS : set the microphone bias voltage
bits : 4 - 6 (3 bit)

SE_VIN_0 : input voltage for VINM[0] / VINP[0]-VINM[0]
bits : 0 - 1 (2 bit)

SE_VIN_1 : input voltage for VINM[1] / VINP[1]-VINM[1]
bits : 2 - 3 (2 bit)

SE_VIN_2 : input voltage for VINM[2] / VINP[2]-VINM[2]
bits : 4 - 5 (2 bit)

SE_VIN_3 : input voltage for VINM[3] / VINP[3]-VINM[3]
bits : 6 - 7 (2 bit)

SE_VIN_4 : input voltage for VINP[0]
bits : 8 - 9 (2 bit)

SE_VIN_5 : input voltage for VINP[1]
bits : 10 - 11 (2 bit)

SE_VIN_6 : input voltage for VINP[2]
bits : 12 - 13 (2 bit)

SE_VIN_7 : input voltage for VINP[3]
bits : 14 - 15 (2 bit)

DF_CIC_DEC_FACTOR :
bits : 0 - 6 (7 bit)

DF_CIC_DHF : CIC filter decimator half factor
bits : 7 - 7 (1 bit)

DF_ITP1P2 : 1.2 fractional interpolator enable
bits : 8 - 8 (1 bit)

DF_I_U2S : select signed/unsigned format for input
bits : 9 - 9 (1 bit)

DF_O_S2U : select signed/unsigned format for data output
bits : 10 - 10 (1 bit)

PDM_RATE : select the PDM clock rate.
bits : 11 - 14 (4 bit)

DF_MICROL_RN : left/right channel selection on digital microphone
bits : 15 - 15 (1 bit)

DF_HPF_EN : high pass filter enable.
bits : 16 - 16 (1 bit)

DF_HALF_D_EN : half dynamic enable.
bits : 17 - 17 (1 bit)

DS_RATIO : program the Down Sampler ratio (N factor)
bits : 0 - 2 (3 bit)

DS_WIDTH : program the Down Sampler width of data output (DSDTATA)
bits : 3 - 5 (3 bit)

SEQ0 : channel number code for first conversion of the sequence
bits : 0 - 3 (4 bit)

SEQ1 : channel number code for second conversion of the sequence.
bits : 4 - 7 (4 bit)

SEQ2 : channel number code for 3rd conversion of the sequence.
bits : 8 - 11 (4 bit)

SEQ3 : channel number code for 4th conversion of the sequence.
bits : 12 - 15 (4 bit)

SEQ4 : channel number code for 5th conversion of the sequence.
bits : 16 - 19 (4 bit)

SEQ5 : channel number code for 6th conversion of the sequence.
bits : 20 - 23 (4 bit)

SEQ6 : channel number code for 7th conversion of the sequence.
bits : 24 - 27 (4 bit)

SEQ7 : channel number code for 8th conversion of the sequence.
bits : 28 - 31 (4 bit)

SEQ8 : channel number code for 9th conversion of the sequence
bits : 0 - 3 (4 bit)

SEQ9 : channel number code for 10th conversion of the sequence.
bits : 4 - 7 (4 bit)

SEQ10 : channel number code for 11th conversion of the sequence.
bits : 8 - 11 (4 bit)

SEQ11 : channel number code for 12th conversion of the sequence.
bits : 12 - 15 (4 bit)

SEQ12 : channel number code for 13th conversion of the sequence.
bits : 16 - 19 (4 bit)

SEQ13 : channel number code for 14th conversion of the sequence.
bits : 20 - 23 (4 bit)

SEQ14 : channel number code for 15th conversion of the sequence.
bits : 24 - 27 (4 bit)

SEQ15 : channel number code for 16th conversion of the sequence.
bits : 28 - 31 (4 bit)

GAIN1 : first calibration point: gain AUXADC_GAIN_1V2[11:0]
bits : 0 - 11 (12 bit)

OFFSET1 : first calibration point: signed offset compensation[6:0]
bits : 12 - 18 (7 bit)

GAIN2 : second calibration point: gain AUXADC_GAIN_1V2[11:0]
bits : 0 - 11 (12 bit)

OFFSET2 : second calibration point: signed offset compensation[6:0]
bits : 12 - 18 (7 bit)

GAIN3 : third calibration point: gain AUXADC_GAIN_1V2[11:0]
bits : 0 - 11 (12 bit)

OFFSET3 : third calibration point: signed offset compensation[6:0]
bits : 12 - 18 (7 bit)

GAIN4 : fourth calibration point: gain AUXADC_GAIN_1V2[11:0]
bits : 0 - 11 (12 bit)

OFFSET4 : fourth calibration point: signed offset compensation[6:0]
bits : 12 - 18 (7 bit)

GAIN_OFFSET0 : gain / offset used in ADC single negative mode with Vinput range = 1.2V
bits : 0 - 1 (2 bit)

GAIN_OFFSET1 : gain / offset used in ADC single positive mode with Vinput range = 1.2V
bits : 2 - 3 (2 bit)

GAIN_OFFSET2 : gain / offset used in ADC differential mode with Vinput range = 1.2V
bits : 4 - 5 (2 bit)

GAIN_OFFSET3 : gain / offset used in ADC single negative mode with Vinput range = 2.4V
bits : 6 - 7 (2 bit)

GAIN_OFFSET4 : gain / offset used in ADC single positive mode with Vinput range = 2.4V
bits : 8 - 9 (2 bit)

GAIN_OFFSET5 : gain / offset used in ADC differential mode with Vinput range = 2.4V
bits : 10 - 11 (2 bit)

GAIN_OFFSET6 : gain / offset used in ADC single negative mode with Vinput range = 3.6V
bits : 12 - 13 (2 bit)

GAIN_OFFSET7 : gain / offset used in ADC single positive mode with Vinput range = 3.6V
bits : 14 - 15 (2 bit)

GAIN_OFFSET8 : gain / offset used in ADC differential mode with Vinput range = 3.6V
bits : 16 - 17 (2 bit)

WD_LT : analog watchdog low level threshold.
bits : 0 - 11 (12 bit)

WD_HT : analog watchdog high level threshold.
bits : 16 - 27 (12 bit)

CONT : regular sequence runs continuously when ADC mode is enabled
bits : 0 - 0 (1 bit)

SEQUENCE : enable the sequence mode (active by default)
bits : 1 - 1 (1 bit)

SEQ_LEN : number of conversions in a regular sequence
bits : 2 - 5 (4 bit)

SMPS_SYNCHRO_ENA : synchronize the ADC start conversion with a pulse generated by the
bits : 6 - 6 (1 bit)

OP_MODE : ADC mode selection (= data path selection)
bits : 7 - 8 (2 bit)

SAMPLE_RATE : conversion rate of ADC
bits : 11 - 12 (2 bit)

DMA_DS_ENA : enable DMA mode for Down Sampler data path
bits : 13 - 13 (1 bit)

DMA_DF_ENA : enable DMA mode for Decimation Filter data path
bits : 14 - 14 (1 bit)

OVR_DS_CFG : Down Sampler overrun configuration
bits : 15 - 15 (1 bit)

OVR_DF_CFG : decimation overrun configuration
bits : 16 - 16 (1 bit)

BIT_INVERT_SN : invert bit to bit the ADC data output when a single
bits : 17 - 17 (1 bit)

BIT_INVERT_DIFF : invert bit to bit the ADC data output when a differential
bits : 18 - 18 (1 bit)

ADC_CONT_1V2 : select the input sampling method
bits : 19 - 19 (1 bit)

VBIAS_PRECH_FORCE : possibility to keep the VBIAS_PRECH enabled to deactivate the filter
bits : 20 - 20 (1 bit)

AWD_CHX : analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog.
bits : 0 - 15 (16 bit)

DS_DATA : contain the converted data at the output of the Down Sampler.
bits : 0 - 15 (16 bit)

DF_DATA : contain the converted data at the output of the decimation filter.
bits : 0 - 15 (16 bit)

EOC_IRQ : (Used in test mode only): set when the ADC conversion is completed.
bits : 0 - 0 (1 bit)

EODS_IRQ : set when the Down Sampler conversion is completed.
bits : 1 - 1 (1 bit)

EODF_IRQ : set when the decimation filter conversion is completed.
bits : 2 - 2 (1 bit)

EOS_IRQ : set when a sequence of conversion is completed.
bits : 3 - 3 (1 bit)

AWD_IRQ : set when an analog watchdog event occurs.
bits : 4 - 4 (1 bit)

OVR_DS_IRQ : set to indicate a Down Sampler overrun (at least one data is lost)
bits : 5 - 5 (1 bit)

OVR_DF_IRQ : set to indicate a decimation filter overrun (a data is lost)
bits : 6 - 6 (1 bit)

DF_OVRFL_IRQ : set to indicate the decimation filter is saturated.
bits : 7 - 7 (1 bit)

EOC_IRQ_ENA : (Used in test mode only): End of ADC conversion interrupt enable
bits : 0 - 0 (1 bit)

EODS_IRQ_ENA : End of conversion interrupt enable for the Down Sampler output
bits : 1 - 1 (1 bit)

EODF_IRQ_ENA : End of conversion interrupt enable for the decimation filter output
bits : 2 - 2 (1 bit)

EOS_IRQ_ENA : End of regular sequence interrupt enable
bits : 3 - 3 (1 bit)

AWD_IRQ_ENA : analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

OVR_DS_IRQ_ENA : Down Sampler overrun interrupt enable
bits : 5 - 5 (1 bit)

OVR_DF_IRQ_ENA : decimation filter overrun interrupt enable
bits : 6 - 6 (1 bit)

DF_OVRFL_IRQ_ENA : decimation filter saturation interrupt enable
bits : 7 - 7 (1 bit)

ADC_LDO_DELAY : define the duration of a waiting time to be inserted between the ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a conversion.
bits : 0 - 7 (8 bit)

VBIAS_PRECH_DELAY : define the duration of a waiting time starting at rising edge of PGA_EN signal and corresponding to the VBIAS precharge duration.
bits : 8 - 15 (8 bit)

PRECH_DELAY_SEL : Select the time step PD_STEP for the VBIAS_PRECH_DELAY timer.
bits : 16 - 16 (1 bit)

ADC_SWITCH_EN : enable individually each connection of the switching matrix at the ADC input, corresponding to AUXADC_INSEL_1V2[15:0].
bits : 0 - 15 (16 bit)

SEL_VIN_TYPE : operation mode of the selected VIN
bits : 18 - 19 (2 bit)

PGA_ENABLE : PGA_ENABLE
bits : 20 - 20 (1 bit)

ADC_RUN : Start/stop ADC conversion.
bits : 21 - 21 (1 bit)

ADC_ENABLE :
bits : 22 - 22 (1 bit)

LDO_ADC_ENABLE :
bits : 23 - 23 (1 bit)

VBIAS_PRECH_ENABLE : set and reset by the software, knowing the bit must stay high at
bits : 24 - 24 (1 bit)

ADC_DBG_CONF : use for debug purpose.
bits : 0 - 3 (4 bit)

DF_DTB_CONF : internal decimation filter multiplexing.
bits : 4 - 7 (4 bit)

ADC_DTB_CONF : configure the DTB output.
bits : 8 - 9 (2 bit)

FSM_STATE : show the state of the state machine.
bits : 16 - 23 (8 bit)

FSM_CUR_STATE : show the last executed state by the state machine.
bits : 24 - 26 (3 bit)

ADC_ON_OFF :
bits : 0 - 0 (1 bit)

START_CON : generate a start pulse to initiate an ADC conversion
bits : 1 - 1 (1 bit)

STOP_OP_MOD : stop the on-going OP_MODE (ADC mode, Analog audio mode, Full
bits : 2 - 2 (1 bit)

DIG_AUD_MODE : enable the digital audio mode (the data path uses the decimation filter)
bits : 3 - 3 (1 bit)

TEST_MODE : select the functional or the test mode of the ADC
bits : 4 - 4 (1 bit)

ADC_LDO_ENA : enable the LDO associated to the ADC block
bits : 5 - 5 (1 bit)

OCM_SRC : select the occasional conversion source
bits : 0 - 0 (1 bit)

OCM_ENA : start occasional conversion in analog audio and full modes
bits : 1 - 1 (1 bit)