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FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x90 byte (0x0)
mem_usage : registers
protection :

Registers

COMMAND

IRQRAW

SIZE

ADDRESS

LFSRVAL

TIMETRIM1

TIMETRIM2

TIMETRIM3

PAGEPROT0

PAGEPROT1

CONFIG

DATA0

DATA1

DATA2

DATA3

IRQSTAT

IRQMASK


COMMAND

Command register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMMAND COMMAND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND

COMMAND : Command opcode to launch any operation on Flash memory. See for command list and detail.
bits : 0 - 7 (8 bit)


IRQRAW

The raw status register shows the unmasked condition of interrupt events.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQRAW IRQRAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDDONE_RIS CMDSTART_RIS CMDERR_RIS ILLCMD_RIS READOK_RIS

CMDDONE_RIS : Command done raw/unmasked interrupt status.
bits : 0 - 0 (1 bit)

CMDSTART_RIS : Command started raw/unmasked interrupt status.
bits : 1 - 1 (1 bit)

CMDERR_RIS : command error raw/unmasked interrupt status.
bits : 2 - 2 (1 bit)

ILLCMD_RIS : Illegal command raw/unmasked interrupt status.
bits : 3 - 3 (1 bit)

READOK_RIS : Mass read OK raw/unmasked interrupt status.
bits : 4 - 4 (1 bit)


SIZE

SIZE register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIZE SIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_SIZE RAM_SIZE FLASH_SECURE SWD_DISABLE

FLASH_SIZE : indicates the last usable address of the Flash using memory component address format.
bits : 0 - 15 (16 bit)

RAM_SIZE : indicates the size of RAM available in the device
bits : 17 - 18 (2 bit)

FLASH_SECURE : indicates the main FLASH is locked by a customer key.
bits : 19 - 19 (1 bit)

SWD_DISABLE : indicates the SWD JTAG is disabled on the device
bits : 20 - 20 (1 bit)


ADDRESS

Address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRESS ADDRESS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YADDR XADDR

YADDR : word number inside the selected row (from 0 to 63)
bits : 0 - 5 (6 bit)

XADDR : page number (from 0 to 127) row number (from 0 to 7)
bits : 6 - 15 (10 bit)


LFSRVAL

Linear Feedback Shift register contains the signature issued by a MASSREAD command.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LFSRVAL LFSRVAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFSRVAL

LFSRVAL : signature after a MASSREAD command, generated through a Linear Feedback Shift Register block
bits : 0 - 31 (32 bit)


TIMETRIM1

Time trim registers 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMETRIM1 TIMETRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_ERASE T_ME T_NVH T_RCV

T_ERASE : Page erase time.
bits : 0 - 7 (8 bit)

T_ME : Mass erase time.
bits : 8 - 15 (8 bit)

T_NVH : NVSTR hold time.
bits : 16 - 23 (8 bit)

T_RCV : Recovery time.
bits : 24 - 31 (8 bit)


TIMETRIM2

Time trim registers 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMETRIM2 TIMETRIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_NVS T_NVH1 T_PROG T_PGS

T_NVS : NVSTR setup time
bits : 0 - 7 (8 bit)

T_NVH1 : NVSTR hold time for mass erase
bits : 8 - 15 (8 bit)

T_PROG : Program time
bits : 16 - 23 (8 bit)

T_PGS : NVSTR to PROGRAM setup time
bits : 24 - 31 (8 bit)


TIMETRIM3

Time trim registers 3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMETRIM3 TIMETRIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_WK

T_WK : Wakeup time.
bits : 0 - 7 (8 bit)


PAGEPROT0

The PAGEPROTx registers allows protecting from accidental write a contiguous set of pages called segment in the following description.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAGEPROT0 PAGEPROT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG0 SEG1

SEG0 : First segment definition.
bits : 0 - 15 (16 bit)

SEG1 : second segment definition.
bits : 16 - 31 (16 bit)


PAGEPROT1

The PAGEPROTx registers allows protecting from accidental write a contiguous set of pages called segment in the following description.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAGEPROT1 PAGEPROT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG2 SEG3

SEG2 : third segment definition.
bits : 0 - 15 (16 bit)

SEG3 : fourth segment definition.
bits : 16 - 31 (16 bit)


CONFIG

Configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LONGACCESS REMAP DIS_GROUP_WRITE PREMAP WAIT_STATES

LONGACCESS : debug and test only
bits : 0 - 0 (1 bit)

REMAP : bit to redirect boot area on SRAM0.
bits : 1 - 1 (1 bit)

DIS_GROUP_WRITE :
bits : 2 - 2 (1 bit)

PREMAP : bit to redirect boot area on IFR or main Flash.
bits : 3 - 3 (1 bit)

WAIT_STATES : Number of wait states to be inserted on Flash read (AHB accesses).
bits : 4 - 5 (2 bit)


DATA0

Data register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA0 DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0

DATA0 : this register has several usage
bits : 0 - 31 (32 bit)


DATA1

Data register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA1 DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1

DATA1 : data that will be written at ADDRESS+1 during a BURSTWRITE command.
bits : 0 - 31 (32 bit)


DATA2

Data register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA2 DATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA2

DATA2 : data that will be written at ADDRESS+2 during a BURSTWRITE command
bits : 0 - 31 (32 bit)


DATA3

Data register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA3 DATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA3

DATA3 : data that will be written at ADDRESS+3 during a BURSTWRITE command.
bits : 0 - 31 (32 bit)


IRQSTAT

The interrupt status register shows the masked version of the interrupt raw register.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSTAT IRQSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDDONE_MIS CMDSTART_MIS CMDERR_MIS ILLCMD_MIS READOK_MIS

CMDDONE_MIS : Command done masked interrupt status.
bits : 0 - 0 (1 bit)

CMDSTART_MIS : Command started masked interrupt status.
bits : 1 - 1 (1 bit)

CMDERR_MIS : command error masked interrupt status.
bits : 2 - 2 (1 bit)

ILLCMD_MIS : Illegal command masked interrupt status.
bits : 3 - 3 (1 bit)

READOK_MIS : Mass read OK masked interrupt status.
bits : 4 - 4 (1 bit)


IRQMASK

The mask bit in IRQMASK will mask the condition in the status register IRQSTAT and prevent the generation of the interrupt.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQMASK IRQMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDDONEM CMDSTARTM CMDERRM ILLCMDM READOKM

CMDDONEM : Command done mask.
bits : 0 - 0 (1 bit)

CMDSTARTM : Command started mask.
bits : 1 - 1 (1 bit)

CMDERRM : command error mask.
bits : 2 - 2 (1 bit)

ILLCMDM : Illegal command mask.
bits : 3 - 3 (1 bit)

READOKM : Mass read OK mask.
bits : 4 - 4 (1 bit)



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