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address_offset : 0x0 Bytes (0x0)
size : 0x90 byte (0x0)
mem_usage : registers
protection :
Command register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMMAND : Command opcode to launch any operation on Flash memory. See for command list and detail.
bits : 0 - 7 (8 bit)
The raw status register shows the unmasked condition of interrupt events.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDDONE_RIS : Command done raw/unmasked interrupt status.
bits : 0 - 0 (1 bit)
CMDSTART_RIS : Command started raw/unmasked interrupt status.
bits : 1 - 1 (1 bit)
CMDERR_RIS : command error raw/unmasked interrupt status.
bits : 2 - 2 (1 bit)
ILLCMD_RIS : Illegal command raw/unmasked interrupt status.
bits : 3 - 3 (1 bit)
READOK_RIS : Mass read OK raw/unmasked interrupt status.
bits : 4 - 4 (1 bit)
SIZE register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASH_SIZE : indicates the last usable address of the Flash using memory component address format.
bits : 0 - 15 (16 bit)
RAM_SIZE : indicates the size of RAM available in the device
bits : 17 - 18 (2 bit)
FLASH_SECURE : indicates the main FLASH is locked by a customer key.
bits : 19 - 19 (1 bit)
SWD_DISABLE : indicates the SWD JTAG is disabled on the device
bits : 20 - 20 (1 bit)
Address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
YADDR : word number inside the selected row (from 0 to 63)
bits : 0 - 5 (6 bit)
XADDR : page number (from 0 to 127) row number (from 0 to 7)
bits : 6 - 15 (10 bit)
Linear Feedback Shift register contains the signature issued by a MASSREAD command.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFSRVAL : signature after a MASSREAD command, generated through a Linear Feedback Shift Register block
bits : 0 - 31 (32 bit)
Time trim registers 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_ERASE : Page erase time.
bits : 0 - 7 (8 bit)
T_ME : Mass erase time.
bits : 8 - 15 (8 bit)
T_NVH : NVSTR hold time.
bits : 16 - 23 (8 bit)
T_RCV : Recovery time.
bits : 24 - 31 (8 bit)
Time trim registers 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_NVS : NVSTR setup time
bits : 0 - 7 (8 bit)
T_NVH1 : NVSTR hold time for mass erase
bits : 8 - 15 (8 bit)
T_PROG : Program time
bits : 16 - 23 (8 bit)
T_PGS : NVSTR to PROGRAM setup time
bits : 24 - 31 (8 bit)
Time trim registers 3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_WK : Wakeup time.
bits : 0 - 7 (8 bit)
The PAGEPROTx registers allows protecting from accidental write a contiguous set of pages called segment in the following description.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG0 : First segment definition.
bits : 0 - 15 (16 bit)
SEG1 : second segment definition.
bits : 16 - 31 (16 bit)
The PAGEPROTx registers allows protecting from accidental write a contiguous set of pages called segment in the following description.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG2 : third segment definition.
bits : 0 - 15 (16 bit)
SEG3 : fourth segment definition.
bits : 16 - 31 (16 bit)
Configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LONGACCESS : debug and test only
bits : 0 - 0 (1 bit)
REMAP : bit to redirect boot area on SRAM0.
bits : 1 - 1 (1 bit)
DIS_GROUP_WRITE :
bits : 2 - 2 (1 bit)
PREMAP : bit to redirect boot area on IFR or main Flash.
bits : 3 - 3 (1 bit)
WAIT_STATES : Number of wait states to be inserted on Flash read (AHB accesses).
bits : 4 - 5 (2 bit)
Data register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : this register has several usage
bits : 0 - 31 (32 bit)
Data register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA1 : data that will be written at ADDRESS+1 during a BURSTWRITE command.
bits : 0 - 31 (32 bit)
Data register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA2 : data that will be written at ADDRESS+2 during a BURSTWRITE command
bits : 0 - 31 (32 bit)
Data register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA3 : data that will be written at ADDRESS+3 during a BURSTWRITE command.
bits : 0 - 31 (32 bit)
The interrupt status register shows the masked version of the interrupt raw register.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDDONE_MIS : Command done masked interrupt status.
bits : 0 - 0 (1 bit)
CMDSTART_MIS : Command started masked interrupt status.
bits : 1 - 1 (1 bit)
CMDERR_MIS : command error masked interrupt status.
bits : 2 - 2 (1 bit)
ILLCMD_MIS : Illegal command masked interrupt status.
bits : 3 - 3 (1 bit)
READOK_MIS : Mass read OK masked interrupt status.
bits : 4 - 4 (1 bit)
The mask bit in IRQMASK will mask the condition in the status register IRQSTAT and prevent the generation of the interrupt.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDDONEM : Command done mask.
bits : 0 - 0 (1 bit)
CMDSTARTM : Command started mask.
bits : 1 - 1 (1 bit)
CMDERRM : command error mask.
bits : 2 - 2 (1 bit)
ILLCMDM : Illegal command mask.
bits : 3 - 3 (1 bit)
READOKM : Mass read OK mask.
bits : 4 - 4 (1 bit)
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