CSR

ISR

IEN

GO : PKA start processing command:

• 0: has no effect.
• 1: starts the processing.

After this bitfield is written to 1, it must be written back to zero manually.
bits : 0 - 0 (1 bit)
access : write-only

READY : PKA readiness status:

• 0: the PKA is computing. It is not ready.
• 1: the PKA is ready to start a new processing.

The rising edge of the READY bit set the PROC_END flag in the ISR register.
bits : 1 - 1 (1 bit)
access : read-only

SFT_RST : PKA software reset:

• 0: has no effect.
• 1: reset the PKA peripheral.

After this bitfield is written to 1, it must be written back to zero manually.
bits : 7 - 7 (1 bit)
access : write-only

PROC_END : PKA process ending interrupt. When read:

• 0: no event.
• 1: PKA process is ended.

When written:

• 0: no effect.
• 1: clears the PKA process ending interrupt.

bits : 0 - 0 (1 bit)

RAM_ERR : RAM read / write access error interrupt. When read:

• 0: All AHB read or write access to the PKA RAM occurred while the PKA was stopped.
• 1: All the AHB read or write access to the PKA RAM occurred while the PKA was operating and using the internal RAM. Those read or write could not succeed as the PKA internal RAM is disconnected from the AHB bus when the PKA is operating (READY bit low).

When written:

• 0: no effect.
• 1: clears the RAM access error interrupt.

bits : 2 - 2 (1 bit)

ADD_ERR : AHB address error interrupt. When read:

• 0: All AHB read or write access to the PKA RAM occurred in a mapped address range.
• 1: All AHB read or write access to the PKA RAM occurred in an unmapped address range.

When written:

• 0: no effect.
• 1: clears the AHB Address error interrupt.

bits : 3 - 3 (1 bit)

READY_EN : READY_EN
bits : 0 - 0 (1 bit)

RAMERR_EN : RAM access error interrupt enable.

• 0: interrupt disabled.
• 1: interrupt enabled.

bits : 2 - 2 (1 bit)

ADDERR_EN : AHB address error interrupt enable.

• 0: interrupt disabled.
• 1: interrupt enabled.

bits : 3 - 3 (1 bit)