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RADIO_CTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

RADIO_CONTROL_ID

RADIO_CONTROL_IRQ_STATUS

RADIO_CONTROL_IRQ_ENABLE

RADIO_CONTROL_SPARE_REG

CLK32COUNT

CLK32PERIOD

CLK32FREQUENCY


RADIO_CONTROL_ID

Radio Controller ID register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RADIO_CONTROL_ID RADIO_CONTROL_ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDENTIFICATION

IDENTIFICATION : IDENTIFICATION
bits : 0 - 31 (32 bit)


RADIO_CONTROL_IRQ_STATUS

Radio Controller Interrupt Status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RADIO_CONTROL_IRQ_STATUS RADIO_CONTROL_IRQ_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW_CLK_IRQ RADIO_FSM_IRQ

LOW_CLK_IRQ : LOW_CLK_IRQ
bits : 0 - 0 (1 bit)

RADIO_FSM_IRQ : RADIO_FSM_IRQ
bits : 8 - 13 (6 bit)


RADIO_CONTROL_IRQ_ENABLE

Radio Controller Interrupt Control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RADIO_CONTROL_IRQ_ENABLE RADIO_CONTROL_IRQ_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOW_CLK_IRQ_MASK RADIO_FSM_IRQ_MASK

SLOW_CLK_IRQ_MASK : SLOW_CLK_IRQ_MASK
bits : 0 - 0 (1 bit)

RADIO_FSM_IRQ_MASK : RADIO_FSM_IRQ_MASK
bits : 8 - 13 (6 bit)


RADIO_CONTROL_SPARE_REG

Radio ControllerSpare register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RADIO_CONTROL_SPARE_REG RADIO_CONTROL_SPARE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLK32COUNT

Window length register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK32COUNT CLK32COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLK32PERIOD

Slow clock period register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK32PERIOD CLK32PERIOD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLK32FREQUENCY

Slow clock frequency register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK32FREQUENCY CLK32FREQUENCY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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