\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Radio Controller ID register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDENTIFICATION : IDENTIFICATION
bits : 0 - 31 (32 bit)
Radio Controller Interrupt Status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW_CLK_IRQ : LOW_CLK_IRQ
bits : 0 - 0 (1 bit)
RADIO_FSM_IRQ : RADIO_FSM_IRQ
bits : 8 - 13 (6 bit)
Radio Controller Interrupt Control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_CLK_IRQ_MASK : SLOW_CLK_IRQ_MASK
bits : 0 - 0 (1 bit)
RADIO_FSM_IRQ_MASK : RADIO_FSM_IRQ_MASK
bits : 8 - 13 (6 bit)
Radio ControllerSpare register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Window length register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Slow clock period register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Slow clock frequency register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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