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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFFF byte (0x0)
mem_usage : registers
protection :

Registers

CR

CIER

CIFR

CSCMDR

AHBRSTR

APB0RSTR

APB1RSTR

ICSCR

APB2RSTR

AHBENR

APB0ENR

APB1ENR

APB2ENR

CFGR

DBGR

CSR

RFSWHSECR

RFHSECR

CSSWCR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY LSEON LSERDY LSEBYP LOCKDET_NSTOP HSIRDY HSEPLLBUFON HSIPLLON HSIPLLRDY FMRAT HSEON HSERDY

LSION : Internal low speed RC clock enable
bits : 2 - 2 (1 bit)
access : read-write

LSIRDY : Internal Low Speed clock flag
bits : 3 - 3 (1 bit)
access : read-only

LSEON : External Low Speed clock enable
bits : 4 - 4 (1 bit)
access : read-write

LSERDY : External Low Speed clock flag
bits : 5 - 5 (1 bit)
access : read-only

LSEBYP : External Low Speed clock bypass.
bits : 6 - 6 (1 bit)
access : read-write

LOCKDET_NSTOP : LOCKDET_NSTOP
bits : 7 - 9 (3 bit)

HSIRDY : HSI clock ready flag
bits : 10 - 10 (1 bit)
access : read-only

HSEPLLBUFON : External high speed clock buffer for PLL RF2G4 enable.
bits : 12 - 12 (1 bit)

HSIPLLON : Internal High Speed clock PLL enable
bits : 13 - 13 (1 bit)
access : read-write

HSIPLLRDY : Internal High Speed clock PLL flag. This bit is set by hardware to indicate that the RC64MPLL pll is locked
bits : 14 - 14 (1 bit)

FMRAT : FMRAT
bits : 15 - 15 (1 bit)

HSEON : External High Speed clock enable.
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : External High Speed clock flag.
bits : 17 - 17 (1 bit)
access : read-only


CIER

Clock interrupt enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIER CIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE HSIPLLRDYIE HSIPLLUNLOCKDETIE RTCRSTIE WDGRSTIE

LSIRDYIE : LSI1 ready interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

HSIRDYIE : HSI ready interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

HSERDYIE : HSE ready interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

HSIPLLRDYIE : HSI PLLSYS ready interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

HSIPLLUNLOCKDETIE : HSI PLL unlock detection interrupt enable.
bits : 6 - 6 (1 bit)

RTCRSTIE : RTC reset release interrupt enable.
bits : 7 - 7 (1 bit)

WDGRSTIE : Watchdog reset release interrupt enable.
bits : 8 - 8 (1 bit)


CIFR

Clock interrupt flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIFR CIFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF HSIPLLRDYF HSIPLLUNLOCKDETF RTCRSTF WDGRSTF

LSIRDYF : LSI1 ready interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)
access : read-write

HSIRDYF : HSI ready interrupt flag
bits : 3 - 3 (1 bit)
access : read-write

HSERDYF : HSE ready interrupt flag
bits : 4 - 4 (1 bit)
access : read-write

HSIPLLRDYF : HSI PLL ready flag
bits : 5 - 5 (1 bit)
access : read-write

HSIPLLUNLOCKDETF : HSI PLL unlock detection flag.
bits : 6 - 6 (1 bit)

RTCRSTF : RTC reset release flag.
bits : 7 - 7 (1 bit)

WDGRSTF : Watchdog reset release flag.
bits : 8 - 8 (1 bit)


CSCMDR

This register allows switching the CPU system clock frequency safely while the MR_BLE is active.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCMDR CSCMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQUEST CLKSYSDIV_REQ STATUS EOFSEQ_IE EOFSEQ_IRQ

REQUEST : Request to switch the system clock frequency.
bits : 0 - 0 (1 bit)

CLKSYSDIV_REQ : System clock requested/targeted frequency.
bits : 1 - 3 (3 bit)

STATUS : Status of the switching sequence.
bits : 4 - 5 (2 bit)

EOFSEQ_IE : End of sequence interrupt enable.
bits : 6 - 6 (1 bit)

EOFSEQ_IRQ : End of sequence flag.
bits : 7 - 7 (1 bit)


AHBRSTR

AHB0 macro cells reset register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRSTR AHBRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARST GPIOARST GPIOBRST CRCRST PKARST RNGRST

DMARST : DMA and DMAMUX reset
bits : 0 - 0 (1 bit)
access : read-write

GPIOARST : IO controller for port B reset
bits : 2 - 2 (1 bit)
access : read-write

GPIOBRST : IO controller for port A reset
bits : 3 - 3 (1 bit)
access : read-write

CRCRST : CRC reset
bits : 12 - 12 (1 bit)
access : read-write

PKARST : PKA reset
bits : 16 - 16 (1 bit)
access : read-write

RNGRST : RNG reset
bits : 18 - 18 (1 bit)
access : read-write


APB0RSTR

APB0 macro cells reset register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB0RSTR APB0RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1RST SYSCFGRST RTCRST WDGRST

TIM1RST : TIM1 reset
bits : 0 - 0 (1 bit)

SYSCFGRST : system controller reset
bits : 8 - 8 (1 bit)

RTCRST : RTC reset
bits : 12 - 12 (1 bit)

WDGRST : Watchdog reset
bits : 14 - 14 (1 bit)


APB1RSTR

APB1 peripheral reset register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR APB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1RST ADCRST LPUARTRST USARTRST SPI2RST SPI3RST I2C1RST I2C2RST

SPI1RST : SPI1 reset
bits : 0 - 0 (1 bit)
access : read-write

ADCRST : ADC reset
bits : 4 - 4 (1 bit)
access : read-write

LPUARTRST : LPUART reset
bits : 8 - 8 (1 bit)
access : read-write

USARTRST : USARTRST: USART reset
bits : 10 - 10 (1 bit)
access : read-write

SPI2RST : SPI2 reset
bits : 12 - 12 (1 bit)
access : read-write

SPI3RST : SPI3 reset
bits : 14 - 14 (1 bit)
access : read-write

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)
access : read-write

I2C2RST : I2C2 reset
bits : 23 - 23 (1 bit)
access : read-write


ICSCR

Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSITRIMEN LSITRIMOK LSIBW HSITRIM

LSITRIMEN : Low speed internal RC trimming enable.
bits : 0 - 0 (1 bit)
access : read-write

LSITRIMOK : Low speed internal RC trimming value is OK.
bits : 1 - 1 (1 bit)
access : read-only

LSIBW : Low speed clock trimming.
bits : 2 - 5 (4 bit)
access : read-only

HSITRIM : High speed clock trimming.
bits : 24 - 29 (6 bit)
access : read-only


APB2RSTR

APB2 peripheral reset register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRBLERST

MRBLERST : MR_BLE Bluetooth radio reset
bits : 0 - 0 (1 bit)
access : read-write


AHBENR

AHB0 macro cells clock enable register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBENR AHBENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN GPIOAEN GPIOBEN CRCEN PKAEN RNGEN

DMAEN : DMA and DMAMUX enable
bits : 0 - 0 (1 bit)
access : read-write

GPIOAEN : IO controller for port A enable
bits : 2 - 2 (1 bit)
access : read-write

GPIOBEN : IO controller for port B enable
bits : 3 - 3 (1 bit)
access : read-write

CRCEN : CRCEN: CRC enable
bits : 12 - 12 (1 bit)
access : read-write

PKAEN : PKAEN: PKA enable
bits : 16 - 16 (1 bit)
access : read-write

RNGEN : RNG clock enable
bits : 18 - 18 (1 bit)
access : read-write


APB0ENR

APB0 macro cells clock enable register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB0ENR APB0ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1EN SYSCFGEN RTCEN WDGEN

TIM1EN : TIM1 enable.
bits : 0 - 0 (1 bit)
access : read-write

SYSCFGEN : system controller enable.
bits : 8 - 8 (1 bit)
access : read-write

RTCEN : RTC enable.
bits : 12 - 12 (1 bit)
access : read-write

WDGEN : Watchdog enable.
bits : 14 - 14 (1 bit)
access : read-write


APB1ENR

APB1ENR
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR APB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1EN ADCDIGEN ADCANAEN LPUARTEN USARTEN SPI2EN SPI3EN I2C1EN I2C2EN

SPI1EN : SPI1 enable
bits : 0 - 0 (1 bit)
access : read-write

ADCDIGEN : ADCDIGEN
bits : 4 - 4 (1 bit)
access : read-write

ADCANAEN : ADCANAEN
bits : 5 - 5 (1 bit)

LPUARTEN : LPUART enable
bits : 8 - 8 (1 bit)
access : read-write

USARTEN : USART enable
bits : 10 - 10 (1 bit)
access : read-write

SPI2EN : SPI2 enable
bits : 12 - 12 (1 bit)
access : read-write

SPI3EN : CPU1 SPI3 clock enable
bits : 14 - 14 (1 bit)
access : read-write

I2C1EN : CPU1 I2C1 clock enable
bits : 21 - 21 (1 bit)
access : read-write

I2C2EN : I2C2 enable
bits : 23 - 23 (1 bit)
access : read-write


APB2ENR

APB2ENR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRBLEEN CLKBLEDIV

MRBLEEN : MR_BLE (Bluetooth radio) enable.
bits : 0 - 0 (1 bit)

CLKBLEDIV : MR_BLE (Bluetooth Low Energy radio) clock frequency selection when RCC_APB2ENR.MRBLEEN=1.
bits : 1 - 2 (2 bit)


CFGR

Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPSINV HSESEL STOPHSI CLKSYSDIV ANADIV SMPSDIV CLKSLOWSEL IOBOOSTEN DBGHSIOFF DBGBYPHSI DBGXOEXT SPI3I2SCLKSEL SPI2I2SCLKSEL LCOSEL MCOSEL CCOPRE

SMPSINV : control inversion of SMPS clock, versus ADC clock
bits : 0 - 0 (1 bit)
access : read-write

HSESEL : Clock source selection request.
bits : 1 - 1 (1 bit)

STOPHSI : RC64MPLL clock source stop request
bits : 2 - 2 (1 bit)

CLKSYSDIV : system clock divided factor from HSI_64M
bits : 5 - 7 (3 bit)
access : read-write

ANADIV : SMPS and ADC clock prescaling factor
bits : 10 - 11 (2 bit)
access : read-write

SMPSDIV : SMPS clock prescaling factor
bits : 12 - 12 (1 bit)
access : read-write

CLKSLOWSEL : low speed clock source selection
bits : 15 - 16 (2 bit)
access : read-write

IOBOOSTEN : IO BOOSTER external clock enable
bits : 17 - 17 (1 bit)
access : read-write

DBGHSIOFF : Used for debug mode only
bits : 19 - 19 (1 bit)
access : read-write

DBGBYPHSI : Used for debug mode only
bits : 20 - 20 (1 bit)
access : read-write

DBGXOEXT : Used for debug mode only
bits : 21 - 21 (1 bit)
access : read-write

SPI3I2SCLKSEL : Selection of I2S clock for SPI2 IP
bits : 22 - 22 (1 bit)
access : read-write

SPI2I2SCLKSEL : Selection of I2S clock for SPI3 IP
bits : 23 - 23 (1 bit)
access : read-write

LCOSEL : Low speed Configurable Clock Output Selection
bits : 24 - 25 (2 bit)
access : read-write

MCOSEL : Microcontroller clock output
bits : 26 - 28 (3 bit)
access : read-write

CCOPRE : Configurable Clock Output Prescaler
bits : 29 - 31 (3 bit)
access : read-write


DBGR

This register is planned for debug use-case only.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGR DBGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGHSIOFF DBGBYPHSI DBGXOEXT

DBGHSIOFF : Used for debug mode only.
bits : 19 - 19 (1 bit)

DBGBYPHSI : Used for debug mode only.
bits : 20 - 20 (1 bit)

DBGXOEXT : Used for debug mode only.
bits : 21 - 21 (1 bit)


CSR

CSR
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMVF PADRSTF PORRSTF SFTRSTF WDGRSTF LOCKUPRSTF

RMVF : Remove Flag reset
bits : 23 - 23 (1 bit)
access : read-write

PADRSTF : NRSTn pad reset flag.
bits : 26 - 26 (1 bit)
access : read-only

PORRSTF : Power-On reset flag
bits : 27 - 27 (1 bit)
access : read-only

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

WDGRSTF : Watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-only

LOCKUPRSTF : CPU lockup reset flag
bits : 30 - 30 (1 bit)
access : read-only


RFSWHSECR

RF Software High Speed External register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFSWHSECR RFSWHSECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SATRG GMC SWXOTUNEEN SWXOTUNE

SATRG : Sense Amplifier Threshold
bits : 3 - 3 (1 bit)

GMC : High speed external IO current control
bits : 4 - 6 (3 bit)

SWXOTUNEEN : RF HSE software capacitor bank tuning enable
bits : 7 - 7 (1 bit)

SWXOTUNE : RF HSE capacitor bank tuning value set by software
bits : 8 - 13 (6 bit)


RFHSECR

RF High Speed External register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RFHSECR RFHSECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOTUNE

XOTUNE : RF-HSE capacitor bank tuning
bits : 0 - 5 (6 bit)


CSSWCR

Clocks Sources Software Calibration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSSWCR CSSWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSISWTRIMEN LSISWBW LSEDRV HSISWTRIMEN HSITRIMSW

LSISWTRIMEN : Low speed internal RC software trimming enable
bits : 0 - 0 (1 bit)
access : read-write

LSISWBW : Low speed internal RC trimming value set by software
bits : 1 - 4 (4 bit)
access : read-write

LSEDRV : external 32 kHz crystal GM
bits : 5 - 6 (2 bit)
access : read-write

HSISWTRIMEN : High speed clock software trimming enable
bits : 23 - 23 (1 bit)
access : read-write

HSITRIMSW : High speed clock trimming set by software
bits : 24 - 29 (6 bit)
access : read-write



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