\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
RRM_ID register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDENTIFICATION : IDENTIFICATION
bits : 0 - 3 (4 bit)
UDRA_CTRL0 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_RDCFGPTR : RELOAD_RDCFGPTR
bits : 0 - 0 (1 bit)
AA0_DIG_USR register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AA_7_0 : AA_7_0
bits : 0 - 7 (8 bit)
AA1_DIG_USR register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AA_15_8 : AA_15_8
bits : 0 - 7 (8 bit)
AA2_DIG_USR register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AA_23_16 : AA_23_16
bits : 0 - 7 (8 bit)
AA3_DIG_USR register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AA_31_24 : AA_31_24
bits : 0 - 7 (8 bit)
DEM_MOD_DIG_USR register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_NUM : CHANNEL_NUM
bits : 1 - 7 (7 bit)
RADIO_FSM_USR register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN_CALIB_CBP : EN_CALIB_CBP
bits : 1 - 1 (1 bit)
EN_CALIB_SYNTH : EN_CALIB_SYNTH
bits : 2 - 2 (1 bit)
PA_POWER : PA_POWER
bits : 3 - 7 (5 bit)
PHYCTRL_DIG_USR register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTXPHY : RXTXPHY
bits : 0 - 2 (3 bit)
SUPPENA : SUPPENA
bits : 3 - 3 (1 bit)
PD_DETECT_MODE : PD_DETECT_MODE
bits : 4 - 4 (1 bit)
PA_CODE1_DIG_ENG register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE_1 : PA_CODE_1
bits : 0 - 7 (8 bit)
PA_CODE2_DIG_ENG register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE_2 : PA_CODE_2
bits : 0 - 7 (8 bit)
PA_CODE3_DIG_ENG register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE_3 : PA_CODE_3
bits : 0 - 7 (8 bit)
PA_CODE4_DIG_ENG register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE_4 : PA_CODE_4
bits : 0 - 7 (8 bit)
PA_CODE5_DIG_ENG register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE_5 : PA_CODE_5
bits : 0 - 7 (8 bit)
PA_CODE6_DIG_ENG register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE_6 : PA_CODE_6
bits : 0 - 7 (8 bit)
PA_CODE7_DIG_ENG register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE_7 : PA_CODE_7
bits : 0 - 7 (8 bit)
PA_DIG_ENG register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_RAMP_STEP_WIDTH : PA_RAMP_STEP_WIDTH
bits : 1 - 2 (2 bit)
LOCK_FAIL_PA_DISABLE : LOCK_FAIL_PA_DISABLE
bits : 5 - 5 (1 bit)
CHECK_LOCK_PA_EXIT_N : CHECK_LOCK_PA_EXIT_N
bits : 6 - 6 (1 bit)
PA_DWN_ANA_EN_N : PA_DWN_ANA_EN_N
bits : 7 - 7 (1 bit)
PA0_ANA_TST register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_ANA_TST_SEL : PA_ANA_TST_SEL
bits : 0 - 0 (1 bit)
RFD_PA_PUP_DRV_1V2 : RFD_PA_PUP_DRV_1V2
bits : 1 - 1 (1 bit)
RFD_PA_PUP_PWCTRL_1V2 : RFD_PA_PUP_PWCTRL_1V2
bits : 2 - 2 (1 bit)
RFD_PA_MAXDBM_1V2 : RFD_PA_MAXDBM_1V2
bits : 3 - 3 (1 bit)
RFD_LDO_TRANSFO_VCEL : RFD_LDO_TRANSFO_VCEL
bits : 4 - 7 (4 bit)
UDRA_IRQ_ENABLE register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RADIO_CFG_PTR_RELOADED : RADIO_CFG_PTR_RELOADED
bits : 0 - 0 (1 bit)
CMD_START : CMD_START
bits : 1 - 1 (1 bit)
CMD_END : CMD_END
bits : 2 - 2 (1 bit)
CMD_NUMBER_ERROR : CMD_NUMBER_ERROR
bits : 3 - 3 (1 bit)
PA1_ANA_TST register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_CODE : PA_CODE
bits : 0 - 7 (8 bit)
AFC0_DIG_ENG register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFC_GAIN_AFTER : AFC_GAIN_AFTER
bits : 0 - 3 (4 bit)
AFC_GAIN_BEFORE : AFC_GAIN_BEFORE
bits : 4 - 7 (4 bit)
AFC1_DIG_ENG register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFC_DELAY_AFTER : AFC_DELAY_AFTER
bits : 0 - 3 (4 bit)
AFC_DELAY_BEFORE : AFC_DELAY_BEFORE
bits : 4 - 7 (4 bit)
AFC2_DIG_ENG register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFC_FREQ_LIMIT : AFC_FREQ_LIMIT
bits : 0 - 6 (7 bit)
AFC_ENABLE : AFC_ENABLE
bits : 7 - 7 (1 bit)
AFC3_DIG_ENG register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFC_MINMAX_LIMIT : AFC_MINMAX_LIMIT
bits : 0 - 7 (8 bit)
CR0_DIG_ENG register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR_GAIN_AFTER : CR_GAIN_AFTER
bits : 0 - 3 (4 bit)
CR_GAIN_BEFORE : CR_GAIN_BEFORE
bits : 4 - 7 (4 bit)
DCF_RSSI_DIG_ENG register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCF_CTRL : DCF_CTRL
bits : 0 - 3 (4 bit)
RSSI_CTRL : RSSI_CTRL
bits : 4 - 7 (4 bit)
AAC0_DIG_ENG register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AAC0_DIG_ENG_SPI : AAC0_DIG_ENG_SPI
bits : 0 - 7 (8 bit)
AAC1_DIG_ENG register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AAC1_DIG_ENG_SPI : AAC1_DIG_ENG_SPI
bits : 0 - 7 (8 bit)
DEMOD_DIG_TST register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TST_DUT : TST_DUT
bits : 1 - 7 (7 bit)
CR0_LR register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR_LR_GAIN_AFTER : CR_LR_GAIN_AFTER
bits : 0 - 3 (4 bit)
CR_LR_GAIN_BEFORE : CR_LR_GAIN_BEFORE
bits : 4 - 7 (4 bit)
VIT_CONF_DIG_ENG register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIT_CONF : VIT_CONF
bits : 0 - 7 (8 bit)
VIT_METR0_DIG_ENG register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIT_METR0 : VIT_METR0
bits : 0 - 7 (8 bit)
VIT_METR1_DIG_ENG register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIT_METR1 : VIT_METR1
bits : 0 - 7 (8 bit)
VIT_METR2_DIG_ENG register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIT_METR2 : VIT_METR2
bits : 0 - 7 (8 bit)
VIT_METR3_DIG_ENG register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIT_METR3 : VIT_METR3
bits : 0 - 7 (8 bit)
UDRA_IRQ_STATUS register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RADIO_CFG_PTR_RELOADED : RADIO_CFG_PTR_RELOADED
bits : 0 - 0 (1 bit)
CMD_START : CMD_START
bits : 1 - 1 (1 bit)
CMD_END : CMD_END
bits : 2 - 2 (1 bit)
CMD_NUMBER_ERROR : CMD_NUMBER_ERROR
bits : 3 - 3 (1 bit)
LR_RSSI_K_DIG_ENG register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LR_RSSI_K : LR_RSSI_K
bits : 0 - 7 (8 bit)
LR_PD_THR_DIG_ENG register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LR_PD_THR : LR_PD_THR
bits : 0 - 7 (8 bit)
LR_RSSI_THR_DIG_ENG register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LR_RSSI_THR : LR_RSSI_THR
bits : 0 - 7 (8 bit)
LR_AAC_THR_DIG_ENG register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LR_AAC_THR : LR_AAC_THR
bits : 0 - 7 (8 bit)
LR_PD_TIMEOUT_DIG_ENG register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LR_PD_TIMEOUT : LR_PD_TIMEOUT
bits : 0 - 7 (8 bit)
LR_AAC_TIMEOUT_DIG_ENG register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LR_AAC_TIMEOUT : LR_AAC_TIMEOUT
bits : 0 - 7 (8 bit)
SYNTHCAL0_ANA_TST register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCO_CALFREQ_EXT : VCO_CALFREQ_EXT
bits : 0 - 6 (7 bit)
VCO_CALFREQ_EXT_SEL : VCO_CALFREQ_EXT_SEL
bits : 7 - 7 (1 bit)
SYNTHCAL1_ANA_TST register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCO_CALAMP_EXT_6_0 : VCO_CALAMP_EXT_6_0
bits : 0 - 6 (7 bit)
VCO_CALAMP_EXT_SEL : VCO_CALAMP_EXT_SEL
bits : 7 - 7 (1 bit)
SYNTHCAL2_ANA_TST register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCO_CALAMP_EXT_10_7 : VCO_CALAMP_EXT_10_7
bits : 0 - 3 (4 bit)
SYNTHCAL3_ANA_TST register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_MOD_REF_DAC_WORD : RFD_MOD_REF_DAC_WORD
bits : 0 - 5 (6 bit)
CALKVCO_EXT_SEL : CALKVCO_EXT_SEL
bits : 7 - 7 (1 bit)
SYNTHCAL0_DIG_ENG register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTHCAL_DEBUG_BUS_SEL : SYNTHCAL_DEBUG_BUS_SEL
bits : 0 - 3 (4 bit)
VCO_ALC_FORCE_PUP : VCO_ALC_FORCE_PUP
bits : 5 - 5 (1 bit)
SYNTH_IF_FREQ_CAL : SYNTH_IF_FREQ_CAL
bits : 6 - 6 (1 bit)
SYNTHCAL1_DIG_ENG register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_DETECT_STOP : LOCK_DETECT_STOP
bits : 0 - 2 (3 bit)
DISABLE_LOCK_DET : DISABLE_LOCK_DET
bits : 3 - 3 (1 bit)
LOCK_DET : LOCK_DET
bits : 4 - 4 (1 bit)
CAL_DIG_TST register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_DIG_TEST_SEL : CAL_DIG_TEST_SEL
bits : 0 - 0 (1 bit)
SYNTHCAL_RESET : SYNTHCAL_RESET
bits : 1 - 1 (1 bit)
SYNTHCAL_CALREQ : SYNTHCAL_CALREQ
bits : 2 - 2 (1 bit)
CBPCAL_START_CAL : CBPCAL_START_CAL
bits : 3 - 3 (1 bit)
SYNTHCAL_SKIP : SYNTHCAL_SKIP
bits : 4 - 4 (1 bit)
EN_CALIB_KVCO : EN_CALIB_KVCO
bits : 5 - 5 (1 bit)
SYNTHCAL2_DIG_ENG register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFSYNTH_RFCOUNTER_7_0 : RFSYNTH_RFCOUNTER_7_0
bits : 0 - 7 (8 bit)
FSM0_DIG_ENG register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMER : RX_TIMER
bits : 0 - 7 (8 bit)
FSM1_DIG_ENG register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDO_SHORT_TIMER : LDO_SHORT_TIMER
bits : 0 - 7 (8 bit)
UDRA_RADIO_CFG_PTR register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RADIO_CONFIG_ADDRESS : RADIO_CONFIG_ADDRESS
bits : 0 - 31 (32 bit)
FSM2_DIG_ENG register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDO_TIMER : LDO_TIMER
bits : 0 - 7 (8 bit)
FSM3_DIG_ENG register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_TIMEOUT : LOCK_TIMEOUT
bits : 0 - 7 (8 bit)
FSM4_DIG_ENG register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBPCAL_TIMEOUT : CBPCAL_TIMEOUT
bits : 0 - 7 (8 bit)
FSM5_DIG_ENG register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTHCAL_TIMEOUT : SYNTHCAL_TIMEOUT
bits : 0 - 7 (8 bit)
FSM6_DIG_ENG register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENA_CURR_TIMEOUT : ENA_CURR_TIMEOUT
bits : 0 - 7 (8 bit)
FSM7_DIG_ENG register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBG_BOOST_TIMEOUT : VBG_BOOST_TIMEOUT
bits : 0 - 7 (8 bit)
FSM8_DIG_ENG register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_DWN_ANA_TIMEOUT : PA_DWN_ANA_TIMEOUT
bits : 0 - 7 (8 bit)
DTB0_DIG_ENG register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTB_EN : DTB_EN
bits : 0 - 0 (1 bit)
DTB_CFG : DTB_CFG
bits : 1 - 4 (4 bit)
DTB1_DIG_ENG register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTB1_CFG : DTB1_CFG
bits : 0 - 6 (7 bit)
DTB1_EN : DTB1_EN
bits : 7 - 7 (1 bit)
DTB2_DIG_ENG register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTB2_CFG : DTB2_CFG
bits : 0 - 7 (8 bit)
DTB3_DIG_ENG register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTB3_CFG : DTB3_CFG
bits : 0 - 7 (8 bit)
DTB4_DIG_ENG register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTB4_CFG : DTB4_CFG
bits : 0 - 2 (3 bit)
DTB5_DIG_ENG register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTX_START_SEL : RXTX_START_SEL
bits : 0 - 0 (1 bit)
TX_ACTIVE : TX_ACTIVE
bits : 1 - 1 (1 bit)
RX_ACTIVE : RX_ACTIVE
bits : 2 - 2 (1 bit)
INITIALIZE : INITIALIZE
bits : 3 - 3 (1 bit)
DTB6_DIG_ENG register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUP_DTB_CFG : WKUP_DTB_CFG
bits : 0 - 1 (2 bit)
WKUP_DTB_EN : WKUP_DTB_EN
bits : 7 - 7 (1 bit)
DTB7_DIG_ENG register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_DTB_CFG : TX_DTB_CFG
bits : 0 - 1 (2 bit)
TX_DTB_EN : TX_DTB_EN
bits : 7 - 7 (1 bit)
DTB8_DIG_ENG register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTB8_CFG : DTB8_CFG
bits : 0 - 7 (8 bit)
SEMA_IRQ_ENABLE register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : LOCK
bits : 0 - 0 (1 bit)
UNLOCK : UNLOCK
bits : 1 - 1 (1 bit)
DTB9_DIG_ENG register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTB9_CFG : DTB9_CFG
bits : 0 - 7 (8 bit)
DTBA_DIG_ENG register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTBA_CFG : DTBA_CFG
bits : 0 - 7 (8 bit)
SYNTH0_ANA_TST register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTH_ANA_TST_SEL : SYNTH_ANA_TST_SEL
bits : 0 - 0 (1 bit)
RFD_PLL_DIV_LDO_PUP : RFD_PLL_DIV_LDO_PUP
bits : 1 - 1 (1 bit)
RFD_PLL_CP_LDO_PUP : RFD_PLL_CP_LDO_PUP
bits : 2 - 2 (1 bit)
RFD_PLL_VCO_LDO_PUP : RFD_PLL_VCO_LDO_PUP
bits : 3 - 3 (1 bit)
RFD_PLL_CP_PUP : RFD_PLL_CP_PUP
bits : 4 - 4 (1 bit)
RFD_PLL_DIV2_PUP : RFD_PLL_DIV2_PUP
bits : 5 - 5 (1 bit)
RFD_PLL_LORX_PUP : RFD_PLL_LORX_PUP
bits : 6 - 6 (1 bit)
RFD_PLL_LOTX_PUP : RFD_PLL_LOTX_PUP
bits : 7 - 7 (1 bit)
SYNTH1_ANA_TST register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_PLL_PFD_PUP : RFD_PLL_PFD_PUP
bits : 1 - 1 (1 bit)
RFD_PLL_PIPELINE_PUP : RFD_PLL_PIPELINE_PUP
bits : 2 - 2 (1 bit)
RFD_PLL_VCO_VREF_PUP : RFD_PLL_VCO_VREF_PUP
bits : 3 - 3 (1 bit)
RFD_PLL_VCO_CORE_PUP : RFD_PLL_VCO_CORE_PUP
bits : 4 - 4 (1 bit)
RFD_PLL_VCO_BUF_PUP : RFD_PLL_VCO_BUF_PUP
bits : 5 - 5 (1 bit)
RFD_PLL_PFD_LD_EN : RFD_PLL_PFD_LD_EN
bits : 6 - 6 (1 bit)
SYNTH0_ANA_ENG register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_PLL_CP_ISEL : RFD_PLL_CP_ISEL
bits : 0 - 2 (3 bit)
RFD_PLL_CP_LDO_BYP : RFD_PLL_CP_LDO_BYP
bits : 3 - 3 (1 bit)
RFD_PLL_CP_SPLIT : RFD_PLL_CP_SPLIT
bits : 4 - 5 (2 bit)
RFD_PLL_VCO_LDO_BYP : RFD_PLL_VCO_LDO_BYP
bits : 6 - 6 (1 bit)
RFD_PLL_VCO_LDO_VCEL : RFD_PLL_VCO_LDO_VCEL
bits : 7 - 7 (1 bit)
SYNTH1_ANA_ENG register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_PLL_FORCE_CMOSDIV_XRST : RFD_PLL_FORCE_CMOSDIV_XRST
bits : 0 - 0 (1 bit)
RFD_PLL_LF_BW_SEL : RFD_PLL_LF_BW_SEL
bits : 1 - 2 (2 bit)
RFD_PLL_LF_HIGH_C1 : RFD_PLL_LF_HIGH_C1
bits : 3 - 3 (1 bit)
RFD_PLL_FREF_EXT_SEL : RFD_PLL_FREF_EXT_SEL
bits : 4 - 4 (1 bit)
RFD_PLL_FCOMP_EXT_SEL : RFD_PLL_FCOMP_EXT_SEL
bits : 5 - 5 (1 bit)
RFD_PLL_DIV_LDO_BYP : RFD_PLL_DIV_LDO_BYP
bits : 6 - 6 (1 bit)
RFD_DISCHBOOSTN : RFD_DISCHBOOSTN
bits : 7 - 7 (1 bit)
SYNTH2_ANA_ENG register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTH3_ANA_ENG register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_PLL_VCO_ALC_AMP : RFD_PLL_VCO_ALC_AMP
bits : 0 - 2 (3 bit)
PLL_BW_BOOST : PLL_BW_BOOST
bits : 3 - 4 (2 bit)
PMU_FORCE_TIMER : PMU_FORCE_TIMER
bits : 7 - 7 (1 bit)
SYNTH_DIG_TST register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTH_DIG_TST_SEL : SYNTH_DIG_TST_SEL
bits : 0 - 0 (1 bit)
PMU_SYNTH_EN : PMU_SYNTH_EN
bits : 1 - 1 (1 bit)
MOD0_ANA_TST register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_ANA_TST_SEL : MOD_ANA_TST_SEL
bits : 0 - 0 (1 bit)
RFD_MOD_ENA_ANA : RFD_MOD_ENA_ANA
bits : 1 - 1 (1 bit)
MOD1_ANA_TST register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_MOD_CALDAC : TX_MOD_CALDAC
bits : 0 - 7 (8 bit)
MOD_ANA_ENG register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_MOD_ENA_D8B : RFD_MOD_ENA_D8B
bits : 0 - 0 (1 bit)
RFD_MOD_ENA_RD6B : RFD_MOD_ENA_RD6B
bits : 1 - 1 (1 bit)
MOD_DIG_ENG register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_MODE : INT_MODE
bits : 0 - 0 (1 bit)
TXMOD_802_DOUBLE : TXMOD_802_DOUBLE
bits : 1 - 1 (1 bit)
FORCE_TX : FORCE_TX
bits : 3 - 3 (1 bit)
EN_DSM : EN_DSM
bits : 4 - 4 (1 bit)
MODDIG_161M_SEL_UPS : MODDIG_161M_SEL_UPS
bits : 5 - 5 (1 bit)
MOD_TYPE : MOD_TYPE
bits : 6 - 7 (2 bit)
MOD0_DIG_TST register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_DIG_TEST_SEL : MOD_DIG_TEST_SEL
bits : 0 - 0 (1 bit)
PMU_NO_MODULTATION : PMU_NO_MODULTATION
bits : 3 - 3 (1 bit)
KFORCE_3_0 : KFORCE_3_0
bits : 4 - 7 (4 bit)
MOD1_DIG_TST register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KFORCE_11_4 : KFORCE_11_4
bits : 0 - 7 (8 bit)
MOD2_DIG_TST register
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KFORCE_19_12 : KFORCE_19_12
bits : 0 - 7 (8 bit)
SEMA_IRQ_STATUS register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : LOCK
bits : 0 - 0 (1 bit)
UNLOCK : UNLOCK
bits : 1 - 1 (1 bit)
MOD3_DIG_TST register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFORCE : AFORCE
bits : 0 - 2 (3 bit)
MFORCE : MFORCE
bits : 3 - 7 (5 bit)
RXADC_ANA_TST register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXADC_ANA_TST_SEL : RXADC_ANA_TST_SEL
bits : 0 - 0 (1 bit)
RFD_RXADC_EN_I : RFD_RXADC_EN_I
bits : 1 - 1 (1 bit)
RFD_RXADC_EN_Q : RFD_RXADC_EN_Q
bits : 2 - 2 (1 bit)
RFD_RXADC_CLK_ENA : RFD_RXADC_CLK_ENA
bits : 3 - 3 (1 bit)
RXADC_ANA_USR register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_RXADC_DELAYTRIM_I : RFD_RXADC_DELAYTRIM_I
bits : 0 - 2 (3 bit)
RFD_RXADC_DELAYTRIM_Q : RFD_RXADC_DELAYTRIM_Q
bits : 3 - 5 (3 bit)
RXADC_ANA_ENG register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_RXADC_CAL_SOC : RFD_RXADC_CAL_SOC
bits : 0 - 0 (1 bit)
RFD_RXADC_CAL_ENA_I : RFD_RXADC_CAL_ENA_I
bits : 1 - 1 (1 bit)
RFD_RXADC_CAL_ENA_Q : RFD_RXADC_CAL_ENA_Q
bits : 2 - 2 (1 bit)
RXADC_CLK_INV : RXADC_CLK_INV
bits : 3 - 3 (1 bit)
LDO_ANA_TST register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDO_ANA_TST_SEL : LDO_ANA_TST_SEL
bits : 0 - 0 (1 bit)
RFD_LDO_TRANSFO_ENA : RFD_LDO_TRANSFO_ENA
bits : 2 - 2 (1 bit)
RFD_LDO_RXADC_ENA : RFD_LDO_RXADC_ENA
bits : 3 - 3 (1 bit)
RFD_LDO_RX_TX_ENA : RFD_LDO_RX_TX_ENA
bits : 4 - 4 (1 bit)
LDO_ANA_ENG register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_LDO_TRANSFO_BYPASS : RFD_LDO_TRANSFO_BYPASS
bits : 1 - 1 (1 bit)
RFD_LDO_RXADC_BYPASS : RFD_LDO_RXADC_BYPASS
bits : 2 - 2 (1 bit)
RFD_LDO_RX_TX_BYPASS : RFD_LDO_RX_TX_BYPASS
bits : 3 - 3 (1 bit)
RX0_ANA_TST register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX0_ANA_TST_SEL : RX0_ANA_TST_SEL
bits : 0 - 0 (1 bit)
RFD_RX_ENA : RFD_RX_ENA
bits : 1 - 1 (1 bit)
RFD_RX_ENA_LNA : RFD_RX_ENA_LNA
bits : 2 - 2 (1 bit)
RFD_RX_ENA_V2I : RFD_RX_ENA_V2I
bits : 3 - 3 (1 bit)
RFD_RX_ENA_CBPFILT : RFD_RX_ENA_CBPFILT
bits : 4 - 4 (1 bit)
RFD_RX_ENA_MIXTIA : RFD_RX_ENA_MIXTIA
bits : 5 - 5 (1 bit)
RFD_RX_ENA_DIV2 : RFD_RX_ENA_DIV2
bits : 6 - 6 (1 bit)
RFD_RX_TRANSFO_IN_RX : RFD_RX_TRANSFO_IN_RX
bits : 7 - 7 (1 bit)
RX1_ANA_TST register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX1_ANA_TST_SEL : RX1_ANA_TST_SEL
bits : 0 - 0 (1 bit)
FD_RX_ENA_CBPCAL : FD_RX_ENA_CBPCAL
bits : 1 - 1 (1 bit)
RFD_RX_CBPCAL_RESET : RFD_RX_CBPCAL_RESET
bits : 2 - 2 (1 bit)
RFD_RX_CBPCAL_SWAP : RFD_RX_CBPCAL_SWAP
bits : 3 - 3 (1 bit)
RFD_RX_CBP_CAP_WORD : RFD_RX_CBP_CAP_WORD
bits : 4 - 7 (4 bit)
RX_ANA_ENG register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_V2I_BOOST : RX_V2I_BOOST
bits : 0 - 0 (1 bit)
RFD_RX_LNA_HSENSI : RFD_RX_LNA_HSENSI
bits : 2 - 2 (1 bit)
RFD_RX_CBPF_GAIN_CTRL : RFD_RX_CBPF_GAIN_CTRL
bits : 4 - 5 (2 bit)
RX_DIG_ENG register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWAP_RXADC_IQ : SWAP_RXADC_IQ
bits : 0 - 0 (1 bit)
INVERT_RXADC_MSB : INVERT_RXADC_MSB
bits : 1 - 1 (1 bit)
TCB0_ANA_ENG register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_TCB_7_0 : RFD_TCB_7_0
bits : 0 - 7 (8 bit)
TCB1_ANA_ENG register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_TCB_8 : RFD_TCB_8
bits : 0 - 0 (1 bit)
TCB2_ANA_ENG register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_TCB_V33 : RFD_TCB_V33
bits : 0 - 5 (6 bit)
RFD_STM : RFD_STM
bits : 6 - 6 (1 bit)
CBIAS0_ANA_ENG register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_CBIAS_IBIAS_TRIM : RFD_CBIAS_IBIAS_TRIM
bits : 0 - 3 (4 bit)
RFD_CBIAS_IPTAT_TRIM : RFD_CBIAS_IPTAT_TRIM
bits : 4 - 7 (4 bit)
CBIAS1_ANA_ENG register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD_CBIAS_VBG_TRIM : RFD_CBIAS_VBG_TRIM
bits : 0 - 3 (4 bit)
RFD_CBIAS_ENA_ATB_CURR : RFD_CBIAS_ENA_ATB_CURR
bits : 4 - 4 (1 bit)
CBIAS_ANA_TEST register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBIAS_ANA_TST_SEL : CBIAS_ANA_TST_SEL
bits : 0 - 0 (1 bit)
RFD_CBIAS_ENA_CORE : RFD_CBIAS_ENA_CORE
bits : 2 - 2 (1 bit)
RFD_CBIAS_ENA_RX_CURR : RFD_CBIAS_ENA_RX_CURR
bits : 3 - 3 (1 bit)
RFD_CBIAS_ENA_TX_CURR : RFD_CBIAS_ENA_TX_CURR
bits : 4 - 4 (1 bit)
RFD_CBIAS_ENA_VBG_BOOST : RFD_CBIAS_ENA_VBG_BOOST
bits : 6 - 6 (1 bit)
RFD_CBIAS_ENA_VBG : RFD_CBIAS_ENA_VBG
bits : 7 - 7 (1 bit)
BLE_IRQ_ENABLE register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_GRANT : PORT_GRANT
bits : 0 - 0 (1 bit)
PORT_RELEASE : PORT_RELEASE
bits : 1 - 1 (1 bit)
PORT_PREEMPT : PORT_PREEMPT
bits : 2 - 2 (1 bit)
PORT_CMD_START : PORT_CMD_START
bits : 3 - 3 (1 bit)
PORT_CMD_END : PORT_CMD_END
bits : 4 - 4 (1 bit)
SYNTHCAL0_DIG_OUT register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VCO_CALAMP_OUT_6_0 : VCO_CALAMP_OUT_6_0
bits : 0 - 6 (7 bit)
SYNTHCAL1_DIG_OUT register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VCO_CALAMP_OUT_10_7 : VCO_CALAMP_OUT_10_7
bits : 0 - 3 (4 bit)
SYNTHCAL2_DIG_OUT register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VCO_CALFREQ_OUT : VCO_CALFREQ_OUT
bits : 0 - 6 (7 bit)
SYNTHCAL3_DIG_OUT register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNTHCAL_DEBUG_BUS : SYNTHCAL_DEBUG_BUS
bits : 0 - 3 (4 bit)
SYNTHCAL4_DIG_OUT register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MOD_REF_DAC_WORD_OUT : MOD_REF_DAC_WORD_OUT
bits : 0 - 5 (6 bit)
SYNTHCAL5_DIG_OUT register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CBP_CALIB_WORD : CBP_CALIB_WORD
bits : 0 - 3 (4 bit)
FSM_STATUS_DIG_OUT register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : STATUS
bits : 0 - 4 (5 bit)
SYNTH_CAL_ERROR : SYNTH_CAL_ERROR
bits : 7 - 7 (1 bit)
IRQ_STATUS_DIG_OUT register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPARE_ANA_OUT register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSSI0_DIG_OUT register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSSI_MEAS_OUT_7_0 : RSSI_MEAS_OUT_7_0
bits : 0 - 7 (8 bit)
RSSI1_DIG_OUT register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSSI_MEAS_OUT_15_8 : RSSI_MEAS_OUT_15_8
bits : 0 - 7 (8 bit)
AGC_DIG_OUT register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AGC_ATT_OUT : AGC_ATT_OUT
bits : 0 - 3 (4 bit)
DEMOD_DIG_OUT register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CI_FIELD : CI_FIELD
bits : 0 - 1 (2 bit)
AAC_FOUND : AAC_FOUND
bits : 2 - 2 (1 bit)
PD_FOUND : PD_FOUND
bits : 3 - 3 (1 bit)
RX_END : RX_END
bits : 4 - 4 (1 bit)
AGC0_ANA_TST register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC0_ANA_TST_SEL : AGC0_ANA_TST_SEL
bits : 0 - 0 (1 bit)
AGC_ANT : AGC_ANT
bits : 1 - 3 (3 bit)
AGC_LNA : AGC_LNA
bits : 4 - 4 (1 bit)
AGC1_ANA_TST register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC1_ANA_TST_SEL : AGC1_ANA_TST_SEL
bits : 0 - 0 (1 bit)
AGC_IFATT : AGC_IFATT
bits : 1 - 5 (5 bit)
AGC2_ANA_TST register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC2_ANA_TST_SEL : AGC2_ANA_TST_SEL
bits : 0 - 0 (1 bit)
AGC_ANTENNAE_USR_TRIM : AGC_ANTENNAE_USR_TRIM
bits : 1 - 3 (3 bit)
BLE_IRQ_STATUS register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_GRANT : PORT_GRANT
bits : 0 - 0 (1 bit)
PORT_RELEASE : PORT_RELEASE
bits : 1 - 1 (1 bit)
PORT_PREEMPT : PORT_PREEMPT
bits : 2 - 2 (1 bit)
CMD_START : CMD_START
bits : 3 - 3 (1 bit)
CMD_END : CMD_END
bits : 4 - 4 (1 bit)
AGC0_DIG_ENG register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_THR_HIGH : AGC_THR_HIGH
bits : 0 - 5 (6 bit)
AGC_ENABLE : AGC_ENABLE
bits : 6 - 6 (1 bit)
AGC1_DIG_ENG register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_THR_LOW_6 : AGC_THR_LOW_6
bits : 0 - 5 (6 bit)
AGC_AUTOLOCK : AGC_AUTOLOCK
bits : 6 - 6 (1 bit)
AGC_LOCK_SYNC : AGC_LOCK_SYNC
bits : 7 - 7 (1 bit)
AGC2_DIG_ENG register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_THR_LOW_12 : AGC_THR_LOW_12
bits : 0 - 5 (6 bit)
AGC3_DIG_ENG register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOLOCK_THR : AUTOLOCK_THR
bits : 0 - 5 (6 bit)
AGC4_DIG_ENG register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_HOLD_TIME_FAST : AGC_HOLD_TIME_FAST
bits : 0 - 3 (4 bit)
AGC_HOLD_TIME_SLOW : AGC_HOLD_TIME_SLOW
bits : 4 - 7 (4 bit)
AGC5_DIG_ENG register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_MEAS : T_MEAS
bits : 0 - 3 (4 bit)
T_INT : T_INT
bits : 4 - 7 (4 bit)
AGC6_DIG_ENG register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOLD_TIME_SEL_10_4 : HOLD_TIME_SEL_10_4
bits : 0 - 6 (7 bit)
AGC7_DIG_ENG register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TH_LOW_SEL_10_4 : TH_LOW_SEL_10_4
bits : 0 - 6 (7 bit)
AGC8_DIG_ENG register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOLD_TIME_SEL_3_0 : HOLD_TIME_SEL_3_0
bits : 0 - 3 (4 bit)
TH_LOW_SEL_3_0 : TH_LOW_SEL_3_0
bits : 4 - 7 (4 bit)
AGC9_DIG_ENG register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START_SEQ : START_SEQ
bits : 0 - 3 (4 bit)
MAX_SEQ : MAX_SEQ
bits : 4 - 7 (4 bit)
AGC10_DIG_ENG register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_0 : ATT_0
bits : 0 - 5 (6 bit)
AGC11_DIG_ENG register
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_1 : ATT_1
bits : 0 - 5 (6 bit)
AGC12_DIG_ENG register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_2 : ATT_2
bits : 0 - 5 (6 bit)
AGC13_DIG_ENG register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_3 : ATT_3
bits : 0 - 5 (6 bit)
AGC14_DIG_ENG register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_4 : ATT_4
bits : 0 - 5 (6 bit)
AGC15_DIG_ENG register
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_5 : ATT_5
bits : 0 - 5 (6 bit)
AGC16_DIG_ENG register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_6 : ATT_6
bits : 0 - 5 (6 bit)
AGC17_DIG_ENG register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_7 : ATT_7
bits : 0 - 5 (6 bit)
AGC18_DIG_ENG register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_8 : ATT_8
bits : 0 - 5 (6 bit)
AGC19_DIG_ENG register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATT_9 : ATT_9
bits : 0 - 5 (6 bit)
AGC20_DIG_ENG register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I_GAIN_COMP : I_GAIN_COMP
bits : 0 - 7 (8 bit)
SPARE_ANA_IN_ENG register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF_ANA_ENG register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSE2ON_TEST : HSE2ON_TEST
bits : 0 - 0 (1 bit)
RESETN_ATB : RESETN_ATB
bits : 1 - 1 (1 bit)
FORCE_XO_READY : FORCE_XO_READY
bits : 2 - 2 (1 bit)
XO32M_ANA_TST register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XO32M_TST_SEL : XO32M_TST_SEL
bits : 0 - 0 (1 bit)
RFD_XO32M_XTCTRLPLL : RFD_XO32M_XTCTRLPLL
bits : 1 - 1 (1 bit)
RXADC_HW_TRIM_OUT register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_RXADC_DELAYTRIM_I : control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR).
bits : 0 - 1 (2 bit)
HW_RXADC_DELAYTRIM_Q : control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR).
bits : 3 - 5 (3 bit)
SPARE : SPARE
bits : 6 - 7 (2 bit)
CBIAS0_HW_TRIM_OUT register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_CBIAS_IBIAS_TRIM : IPTAT current (provided by the HW trimming, automatically loaded on POR).
bits : 0 - 3 (4 bit)
HW_CBIAS_IPTAT_TRIM : IPTAT current (provided by the HW trimming, automatically loaded on POR).
bits : 4 - 7 (4 bit)
CBIAS1_HW_TRIM_OUT register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_CBIAS_VBG_TRIM : VBG current (provided by the HW trimming, automatically loaded on POR).
bits : 0 - 2 (3 bit)
RRM_CTRL register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY : PRIORITY
bits : 0 - 1 (2 bit)
VP_CPU_CMD_BUS register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMMAND : COMMAND
bits : 0 - 2 (3 bit)
COMMAND_REQ : COMMAND_REQ
bits : 3 - 3 (1 bit)
VP_CPU_SEMA_BUS register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAKE_PRIO : TAKE_PRIO
bits : 0 - 2 (3 bit)
TAKE_REQ : TAKE_REQ
bits : 3 - 3 (1 bit)
TAKE_PREEMPT : TAKE_PREEMPT
bits : 4 - 4 (1 bit)
VP_CPU_IRQ_ENABLE register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_GRANT : PORT_GRANT
bits : 0 - 0 (1 bit)
PORT_RELEASE : PORT_RELEASE
bits : 1 - 1 (1 bit)
PORT_PREEMPT : PORT_PREEMPT
bits : 2 - 2 (1 bit)
PORT_CMD_START : PORT_CMD_START
bits : 3 - 3 (1 bit)
PORT_CMD_END : PORT_CMD_END
bits : 4 - 4 (1 bit)
VP_CPU_IRQ_STATUS register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_GRANT : PORT_GRANT
bits : 0 - 0 (1 bit)
PORT_RELEASE : PORT_RELEASE
bits : 1 - 1 (1 bit)
PORT_PREEMPT : PORT_PREEMPT
bits : 2 - 2 (1 bit)
CMD_START : CMD_START
bits : 3 - 3 (1 bit)
CMD_END : CMD_END
bits : 4 - 4 (1 bit)
RRM test register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRM_SPARE register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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