\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :
This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASTER_MODE : This bit controls whether the I2C master is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
master disabled
1 : Enable
master enabled
End of enumeration elements list.
SPEED : These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software.
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
1 : Standard Mode
standard mode (0 to 100 kbit/s)
2 : Fast Mode
fast mode (less than or equal 400 kbit/s)
3 : High Speed Mode
high speed mode (less than or equal 3.4 Mbit/s)
End of enumeration elements list.
IC_10BITADDR_SLAVE : When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared
1 : Enable
10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
End of enumeration elements list.
IC_10BITADDR_MASTER_RD_ONLY : the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Disable
7-bit addressing
1 : Enable
10-bit addressing
End of enumeration elements list.
IC_RESTART_EN : Determines whether RESTART conditions may be sent when acting as a master
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
IC_SLAVE_DISABLE : This bit controls whether I2C has its slave disabled
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
slave is enabled
1 : Enable
slave is disabled
End of enumeration elements list.
STOP_DET_IFADDRESSED : The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Issues the STOP DETECTION irrespective of whether it is addressed or not.
1 : Enable
issues the STOP DETECTION interrupt only when it is addressed.
End of enumeration elements list.
TX_EMPTY_CTRL : This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register.
bits : 8 - 16 (9 bit)
access : read-write
RESERVED1 : reserved1
bits : 9 - 18 (10 bit)
access : read-only
STOP_DET_IF_MASTER_ACTIVE : In Master mode.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Issues the STOP_DET irrespective of whether the master is active.
1 : Enable
Issues the STOP_DET interrupt only when the master is active
End of enumeration elements list.
BUS_CLEAR_FEATURE_CTRL : In Master mode.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
Bus Clear Feature is disabled
1 : Enable
Bus Clear Feature is enabled
End of enumeration elements list.
RESERVED2 : reserved2
bits : 12 - 43 (32 bit)
access : read-write
I2C Rx/Tx Data Buffer and Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : This register contains the data to be transmitted or received on the I2C bus
bits : 0 - 7 (8 bit)
access : read-write
CMD : This bit controls whether a read or a write is performed
bits : 8 - 16 (9 bit)
access : write-only
Enumeration:
0 : Disable
write
1 : Enable
Read
End of enumeration elements list.
STOP : This bit controls whether a STOP is issued after the byte is sent or received
bits : 9 - 18 (10 bit)
access : write-only
Enumeration:
0 : Disable
STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty
1 : Enable
STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty
End of enumeration elements list.
RESTART : This bit controls whether a RESTART is issued before the byte is sent or received
bits : 10 - 20 (11 bit)
access : write-only
Enumeration:
0 : Disable
If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command
1 : Enable
If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received
End of enumeration elements list.
FIRST_DATA_BYTE : Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode
bits : 11 - 22 (12 bit)
access : read-only
RESERVED1 : reserved1
bits : 12 - 43 (32 bit)
access : read-only
Standard Speed I2C Clock SCL High Count Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_SS_SCL_HCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Standard Speed I2C Clock SCL Low Count Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_SS_SCL_LCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Fast Speed I2C Clock SCL High Count Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_FS_SCL_HCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Fast Speed I2C Clock SCL Low Count Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_FS_SCL_LCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
High Speed I2C Clock SCL High Count Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_HS_SCL_HCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
High Speed I2C Clock SCL Low Count Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_HS_SCL_LCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
I2C Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R_RX_UNDER : Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
bits : 0 - 0 (1 bit)
access : read-only
R_RX_OVER : Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
bits : 1 - 2 (2 bit)
access : read-only
R_RX_FULL : Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
bits : 2 - 4 (3 bit)
access : read-only
R_TX_OVER : Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
bits : 3 - 6 (4 bit)
access : read-only
R_TX_EMPTY : This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
bits : 4 - 8 (5 bit)
access : read-only
R_RD_REQ : This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
bits : 5 - 10 (6 bit)
access : read-only
R_TX_ABRT : This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
bits : 6 - 12 (7 bit)
access : read-only
R_RX_DONE : When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
bits : 7 - 14 (8 bit)
access : read-only
R_ACTIVITY : This bit captures DW_apb_i2c activity and stays set until it is cleared
bits : 8 - 16 (9 bit)
access : read-only
R_STOP_DET : Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
bits : 9 - 18 (10 bit)
access : read-only
R_START_DET : Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
bits : 10 - 20 (11 bit)
access : read-only
R_GEN_CALL : Set only when a General Call address is received and it is acknowledged
bits : 11 - 22 (12 bit)
access : read-only
R_RESTART_DET : Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
bits : 12 - 24 (13 bit)
access : read-only
R_MST_ON_HOLD : Indicates whether a master is holding the bus and the Tx FIFO is empty.
bits : 13 - 26 (14 bit)
access : read-only
M_SCL_STUCK_AT_LOW : Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
bits : 14 - 28 (15 bit)
access : read-only
RESERVED1 : reserved1
bits : 15 - 46 (32 bit)
access : read-only
I2C Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_RX_UNDER : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-write
M_RX_OVER : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 1 - 2 (2 bit)
access : read-write
M_RX_FULL : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 2 - 4 (3 bit)
access : read-write
M_TX_OVER : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register
bits : 3 - 6 (4 bit)
access : read-write
M_TX_EMPTY : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 4 - 8 (5 bit)
access : read-write
M_RD_REQ : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 5 - 10 (6 bit)
access : read-write
M_TX_ABRT : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 6 - 12 (7 bit)
access : read-write
M_RX_DONE : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 7 - 14 (8 bit)
access : read-write
M_ACTIVITY : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 8 - 16 (9 bit)
access : read-write
M_STOP_DET : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 9 - 18 (10 bit)
access : read-write
M_START_DET : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 10 - 20 (11 bit)
access : read-write
M_GEN_CALL : This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
bits : 11 - 22 (12 bit)
access : read-write
M_RESTART_DET : Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
bits : 12 - 24 (13 bit)
access : read-write
M_MST_ON_HOLD : Indicates whether a master is holding the bus and the Tx FIFO is empty.
bits : 13 - 26 (14 bit)
access : read-write
M_SCL_STUCK_AT_LOW : Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
bits : 14 - 28 (15 bit)
access : read-only
RESERVED1 : reserved1
bits : 15 - 46 (32 bit)
access : read-only
I2C Raw Interrupt Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_UNDER : Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
bits : 0 - 0 (1 bit)
access : read-only
RX_OVER : Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
bits : 1 - 2 (2 bit)
access : read-only
RX_FULL : Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
bits : 2 - 4 (3 bit)
access : read-only
TX_OVER : Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
bits : 3 - 6 (4 bit)
access : read-only
TX_EMPTY : This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
bits : 4 - 8 (5 bit)
access : read-only
RD_REQ : This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
bits : 5 - 10 (6 bit)
access : read-only
TX_ABRT : This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
bits : 6 - 12 (7 bit)
access : read-only
RX_DONE : When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
bits : 7 - 14 (8 bit)
access : read-only
ACTIVITY : This bit captures DW_apb_i2c activity and stays set until it is cleared
bits : 8 - 16 (9 bit)
access : read-only
STOP_DET : Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
bits : 9 - 18 (10 bit)
access : read-only
START_DET : Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
bits : 10 - 20 (11 bit)
access : read-only
GEN_CALL : Set only when a General Call address is received and it is acknowledged
bits : 11 - 22 (12 bit)
access : read-only
RESTART_DET : Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
bits : 12 - 24 (13 bit)
access : read-only
MST_ON_HOLD : Indicates whether a master is holding the bus and the Tx FIFO is empty.
bits : 13 - 26 (14 bit)
access : read-only
SCL_STUCK_AT_LOW : Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
bits : 14 - 28 (15 bit)
access : read-only
RESERVED1 : reserved1
bits : 15 - 46 (32 bit)
access : read-only
I2C Receive FIFO Threshold Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TL : Receive FIFO Threshold Level
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
I2C Transmit FIFO Threshold Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_TL : Transmit FIFO Threshold Level
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
I2C Target Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_TAR : This is the target address for any master transaction
bits : 0 - 9 (10 bit)
access : read-write
GC_OR_START : If bit 11 (SPECIAL) is set to 1 and bit 13 (Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the I2C
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
The I2C remains in General Call mode until the SPECIAL bit value (bit 11) is cleared
1 : Enable
START BYTE
End of enumeration elements list.
SPECIAL : This bit indicates whether software performs a General Call or START BYTE command
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
ignore bit 10 GC_OR_START and use IC_TAR normally
1 : Enable
perform special I2C command as specified in GC_OR_START bit
End of enumeration elements list.
IC_10BITADDR_MASTER : This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
7-bit addressing
1 : Enable
10-bit addressing
End of enumeration elements list.
DEVICE_ID : If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
Device-ID is not performed and checks ic_tar[10] to perform either general call or START byte command.
1 : Enable
: Device-ID transfer is performed and bytes based on the number of read commands in the Tx-FIFO are received from the targeted slave and put in the Rx-FIFO.
End of enumeration elements list.
RESERVED1 : reserved1
bits : 14 - 45 (32 bit)
access : read-only
Clear Combined and Individual Interrupt Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_INTR : Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear RX_UNDER Interrupt Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_RX_UNDER : Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear RX_OVER Interrupt Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_RX_OVER : Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear TX_OVER Interrupt Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_TX_OVER : Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear RD_REQ Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_RD_REQ : Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear TX_ABRT Interrupt Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_TX_ABRT : Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear RX_DONE Interrupt Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_RX_DONE : Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear ACTIVITY Interrupt Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_ACTIVITY : Reading this register clears the ACTIVITY interrupt if the I2C is not active any more
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear STOP_DET Interrupt Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_STOP_DET : Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear START_DET Interrupt Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_START_DET : Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear GEN_CALL Interrupt Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_GEN_CALL : Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Clear GEN_CALL Interrupt Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Controls whether the DW_apb_i2c is enabled
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state)
1 : Enable
Enables DW_apb_i2c
End of enumeration elements list.
ABORT : When set, the controller initiates the transfer abort
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
ABORT not initiated or ABORT done
1 : Enable
ABORT operation in progress
End of enumeration elements list.
TX_CMD_BLOCK : none
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
1 : Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
End of enumeration elements list.
SDA_STUCK_RECOVERY_ENABLE : If SDA is stuck at low indicated through the TX_ABORT interrupt IC_TX_ABRT_SOURCE17, then this bit is used as a control knob to initiate the SDA Recovery Mechanism
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
1 : Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
End of enumeration elements list.
RESERVED1 : reserved1
bits : 4 - 19 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
I2C Status Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVITY : I2C Activity Status
bits : 0 - 0 (1 bit)
access : read-only
TFNF : Transmit FIFO Not Full
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : Disable
Transmit FIFO is full
1 : Enable
Transmit FIFO is not full
End of enumeration elements list.
TFE : Transmit FIFO Completely Empty
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : Disable
Transmit FIFO is not empty
1 : Enable
Transmit FIFO is empty
End of enumeration elements list.
RFNE : Receive FIFO Not Empty
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : Disable
Receive FIFO is not empty
1 : Enable
Receive FIFO is not empty
End of enumeration elements list.
RFF : Receive FIFO Completely Full
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Disable
Receive FIFO is not full
1 : Enable
Receive FIFO is full
End of enumeration elements list.
MST_ACTIVITY : Master FSM Activity Status
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : Disable
Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active
1 : Enable
Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active
End of enumeration elements list.
SLV_ACTIVITY : Slave FSM Activity Status
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : Disable
Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active
1 : Enable
Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active
End of enumeration elements list.
MST_HOLD_TX_FIFO_EMPTY : The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set.
bits : 7 - 14 (8 bit)
access : read-only
MST_HOLD_RX_FIFO_FULL : This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received.
bits : 8 - 16 (9 bit)
access : read-only
SLV_HOLD_TX_FIFO_EMPTY : This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty.
bits : 9 - 18 (10 bit)
access : read-only
SLV_HOLD_RX_FIFO_FULL : This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received.
bits : 10 - 20 (11 bit)
access : read-only
SDA_STUCK_NOT_RECOVERED : This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism.
bits : 11 - 22 (12 bit)
access : read-only
RESERVED1 : reserved1
bits : 12 - 43 (32 bit)
access : read-only
I2C Transmit FIFO Level Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFLR : Contains the number of valid data entries in the transmit FIFO.
bits : 0 - 3 (4 bit)
access : read-only
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only
I2C Receive FIFO Level Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXFLR : Receive FIFO Level. Contains the number of valid data entries in the receive FIFO
bits : 0 - 3 (4 bit)
access : read-only
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only
I2C SDA Hold Time Length Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_SDA_TX_HOLD : Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter.
bits : 0 - 15 (16 bit)
access : read-write
IC_SDA_RX_HOLD : Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver.
bits : 16 - 39 (24 bit)
access : read-write
RESERVED1 : reserved1
bits : 24 - 55 (32 bit)
access : read-only
I2C Slave Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_SAR : The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
bits : 0 - 9 (10 bit)
access : read-write
RESERVED1 : reserved1
bits : 10 - 41 (32 bit)
access : read-only
I2C Transmit Abort Source Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ABRT_7B_ADDR_NOACK : 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave
bits : 0 - 0 (1 bit)
access : read-only
ABRT_10ADDR1_NOACK : 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave
bits : 1 - 2 (2 bit)
access : read-only
ABRT_10ADDR2_NOACK : 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave
bits : 2 - 4 (3 bit)
access : read-only
ABRT_TXDATA_NOACK : 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s)
bits : 3 - 6 (4 bit)
access : read-only
ABRT_GCALL_NOACK : 1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call
bits : 4 - 8 (5 bit)
access : read-only
ABRT_GCALL_READ : 1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)
bits : 5 - 10 (6 bit)
access : read-only
ABRT_HS_ACKDET : 1: Master is in High Speed mode and the High Speed Master code was acknowledged
bits : 6 - 12 (7 bit)
access : read-only
ABRT_SBYTE_ACKDET : 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)
bits : 7 - 14 (8 bit)
access : read-only
ABRT_HS_NORSTRT : 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode
bits : 8 - 16 (9 bit)
access : read-only
ABRT_SBYTE_NORSTRT : 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte
bits : 9 - 18 (10 bit)
access : read-only
ABRT_10B_RD_NORSTRT : 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode
bits : 10 - 20 (11 bit)
access : read-only
ABRT_MASTER_DIS : 1: User tries to initiate a Master operation with the Master mode disabled
bits : 11 - 22 (12 bit)
access : read-only
ARB_LOST : 1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration
bits : 12 - 24 (13 bit)
access : read-only
ABRT_SLVFLUSH_TXFIFO : 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO
bits : 13 - 26 (14 bit)
access : read-only
ABRT_SLV_ARBLOST : 1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time
bits : 14 - 28 (15 bit)
access : read-only
ABRT_SLVRD_INTX : 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register
bits : 15 - 30 (16 bit)
access : read-only
ABRT_USER_ABRT : This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]).
bits : 16 - 32 (17 bit)
access : read-only
ABRT_SDA_STUCK_AT_LOW : Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks
bits : 17 - 34 (18 bit)
access : read-only
ABRT_DEVICE_NOACK : Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave
bits : 18 - 36 (19 bit)
access : read-only
ABRT_DEVICE_SLVADDR_NOACK : Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave
bits : 19 - 38 (20 bit)
access : read-only
ABRT_DEVICE_WRITE : Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands.
bits : 20 - 40 (21 bit)
access : read-only
RESERVED1 : reserved1
bits : 21 - 43 (23 bit)
access : read-only
TX_FLUSH_CNT : This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt
bits : 23 - 54 (32 bit)
access : read-only
Generate Slave Data NACK Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NACK : Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver.
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
DMA Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDMAE : Receive DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Receive DMA disabled
1 : Enable
Receive DMA enabled
End of enumeration elements list.
TDMAE : Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Transmit DMA disabled
1 : Enable
Transmit DMA enabled
End of enumeration elements list.
RESERVED1 : reserved1
bits : 2 - 33 (32 bit)
access : read-only
DMA Transmit Data Level Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATDL : This bit field controls the level at which a DMA request is made by the transmit logic
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only
I2C Receive Data Level Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMARDL : This bit field controls the level at which a DMA request is made by the receive logic
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only
I2C SDA Setup Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDA_SETUP : This register controls the amount of time delay (in terms of number of ic_clk clock periods)
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
I2C ACK General Call Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACK_GEN_CALL : ACK General Call
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
DW_apb_i2c does not generate General Call interrupts
1 : Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
I2C Enable Status Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACK_GEN_CALL : ACK General Call
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
DW_apb_i2c does not generate General Call interrupts
1 : Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
End of enumeration elements list.
SLV_DISABLED_WHILE_BUSY : This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : Disable
DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
1 : Enable
DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer
End of enumeration elements list.
SLV_RX_DATA_LOST : Slave Received Data Lost
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : Disable
DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK
1 : Enable
DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer
End of enumeration elements list.
RESERVED1 : reserved1
bits : 3 - 34 (32 bit)
access : read-write
I2C SS and FS Spike Suppression Limit Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : IC_UFM_SPKLEN
reset_Mask : 0x0
IC_FS_SPKLEN : This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
I2C HS Spike Suppression Limit Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_HS_SPKLEN : This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Clear RESTART_DET Interrupt Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_RESTART_DET : Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
I2C SCL Stuck at Low Timeout
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
IC_SCL_STUCK_LOW_TIMEOUT : Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period
bits : 0 - 31 (32 bit)
access : read-write
I2C SDA Stuck at Low Timeout
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
IC_SDA_STUCK_LOW_TIMEOUT : Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period.
bits : 0 - 31 (32 bit)
access : read-write
Clear SCL Stuck at Low Detect Interrupt Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
CLR_SCL_STUCK : Read this register to clear the SCL_STUCK_DET interrupt
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
I2C Device ID
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DEVICE_ID : Contains the Device-ID of the component assigned through the configuration parameter
bits : 0 - 23 (24 bit)
access : read-only
RESERVED1 : reserved1
bits : 24 - 55 (32 bit)
access : read-only
SMBUS Slave Clock Extend Timeout Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMBUS_CLK_LOW_SEXT_TIMEOUT : The values in this register are in units of ic_clk period.
bits : 0 - 31 (32 bit)
access : read-write
I2C High Speed Master Mode Code Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_HS_MAR : This bit field holds the value of the I2C HS mode master code
bits : 0 - 2 (3 bit)
access : read-write
RESERVED1 : reserved1
bits : 3 - 34 (32 bit)
access : read-only
SMBUS Master extend clock Timeout Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMBUS_CLK_LOW_MEXT_TIMEOUT : The values in this register are in units of ic_clk period..
bits : 0 - 31 (32 bit)
access : read-write
SMBus Thigh MAX Bus-Idle count Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMBUS_THIGH_MAX_BUS_IDLE_CNT : The values in this register are in units of ic_clk period.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
SMBUS Interrupt Status Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED1 : Reserved1
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Mask Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED1 : Reserved1
bits : 0 - 31 (32 bit)
access : read-write
SMBUS Raw Interrupt Status Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED1 : Reserved1.
bits : 0 - 31 (32 bit)
access : read-write
Clear SMBUS Interrupt Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED1 : RESERVED1
bits : 0 - 31 (32 bit)
access : read-write
Optional Slave Address Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED1 : Reserved1.
bits : 0 - 31 (32 bit)
access : read-write
SMBUS ARP UDID LSB Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC_SMBUS_ARP_UDID_LSB : This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol.
bits : 0 - 31 (32 bit)
access : read-write
I2C HS Spike Suppression Limit Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLR_RESTART_DET : Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
bits : 0 - 0 (1 bit)
access : read-only
MAX_SPEED_MODE : Maximum Speed Mode
bits : 2 - 5 (4 bit)
access : read-only
Enumeration:
0x0 : NONE
none
0x1 : Standard
Standard
0x2 : Fast
Fast
0x3 : High
High
End of enumeration elements list.
HC_COUNT_VALUES : Hard Code the count values
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0x0 : False
False
0x1 : True
True
End of enumeration elements list.
INTR_IO : Single Interrupt Output port
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0x0 : Individual
Individual
0x1 : Combined
Combined
End of enumeration elements list.
HAS_DMA : DMA Handshake Interface signal
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0x0 : False
False
0x1 : True
True
End of enumeration elements list.
ADD_ENCODED_PARAMS : Add Encoded Parameters
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0x0 : False
False
0x1 : True
True
End of enumeration elements list.
RX_BUFFER_DEPTH : Depth of receive buffer the buffer is 8 bits wide 2 to 256
bits : 8 - 23 (16 bit)
access : read-only
TX_BUFFER_DEPTH : Depth of Transmit buffer the buffer is 8 bits wide 2 to 256
bits : 16 - 39 (24 bit)
access : read-only
RESERVED1 : reserved1
bits : 24 - 55 (32 bit)
access : read-only
I2C Component Version Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
IC_COMP_VERSION : Signifies the component version
bits : 0 - 31 (32 bit)
access : read-only
I2C Component Type Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
IC_COMP_TYPE : Design ware Component Type number = 0x44_57_01_40
bits : 0 - 31 (32 bit)
access : read-only
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