Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14C byte (0x0)
mem_usage : registers
protection :
PWM_DEADTIME_PRESCALE_SELECT_A
PWM_DEADTIME_PRESCALE_SELECT_B
PWM_OP_OVERRIDE_CTRL_RESET_REG
PWM_OP_OVERRIDE_ENABLE_SET_REG
PWM_OP_OVERRIDE_ENABLE_RESET_REG
PWM_OP_OVERRIDE_VALUE_RESET_REG
PWM_FLT_OVERRIDE_CTRL_RESET_REG
PWM Interrupt Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 : This time base interrupt for 0th channel without considering postscaler
bits : 0 - 0 (1 bit)
access : read-only
PWM_TIME_PRD_MATCH_INTR_CH0 : This time base interrupt for 0th channel, which considers postscaler value
bits : 1 - 2 (2 bit)
access : read-only
FLT_A_INTR : When the fault A pin is driven low, this interrupt is raised.
bits : 2 - 4 (3 bit)
access : read-only
FLT_B_INTR : When the fault B pin is driven low, this interrupt is raised.
bits : 3 - 6 (4 bit)
access : read-only
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 : This time base interrupt for 1st channel without considering postscaler value
bits : 4 - 8 (5 bit)
access : read-only
PWM_TIME_PRD_MATCH_INTR_CH1 : This time base interrupt for 1st channel, which considers postscaler value.
bits : 5 - 10 (6 bit)
access : read-only
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 : This time base interrupt for 2nd channel without considering postscaler value.
bits : 6 - 12 (7 bit)
access : read-only
PWM_TIME_PRD_MATCH_INTR_CH2 : This time base interrupt for 2nd channel, which considers postscaler value
bits : 7 - 14 (8 bit)
access : read-only
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 : This time base interrupt for 3rd channel without considering postscaler value.
bits : 8 - 16 (9 bit)
access : read-only
PWM_TIME_PRD_MATCH_INTR_CH3 : This time base interrupt for 3rd channel, which considers postscaler value.
bits : 9 - 18 (10 bit)
access : read-only
RESERVED1 : reserved1
bits : 10 - 41 (32 bit)
access : read-only
PWM deadtime for A and channel varies from 0 to 3
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEADTIME_A_CH : Dead time A value to load into dead time counter A of channel0 to channel3
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : reserved1
bits : 6 - 37 (32 bit)
access : read-write
Base timer period register of channel1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_REG_WR_VALUE_CH1 : Value to update the base timer period register of channel 1
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Base time counter initial value register for channel1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_WR_REG_CH1 : To update the base time counter initial value for channel 1
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
NONE
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_OPEARATING_MODE_CH1 : Base timer operating mode for channel1
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FREE_RUNNING_MODE
free running mode
1 : SINGLE_EVENT_MODE
single event mode
2 : DOWN_COUNT_MODE
down count mode
3 : NONE1
none1
4 : UP_DOWN_MODE
up/down mode
5 : UP_DOWN_DOUBLER_MODE
up/dowm mode with interrupts for double PWM updates
6 : NONE2
none2
7 : NONE3
none3
End of enumeration elements list.
RESERVED1 : reserved1
bits : 3 - 6 (4 bit)
access : read-write
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 : Base timer input clock prescale select value for channel1.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : 1x_clock_period
1x input clock period
1 : 2x_clock_period
2x input clock period
2 : 4x_clock_period
4x input clock period
3 : 16x_clock_period
16x input clock period
4 : 32x_clock_period
32x input clock period
5 : NONE1
none2
6 : 64x_clock_period
64x input clock period
7 : NONE2
none1
End of enumeration elements list.
RESERVED2 : reserved2
bits : 7 - 14 (8 bit)
access : read-write
PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 : Time base output post scale bits for channel1
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : 1:1_post_scale
0000 1:1 post scale
1 : 1:2_post_scale
0001 1:2
2 : 1:3_post_scale
0010 1:3
3 : 1:4_post_scale
0011 1:4
4 : 1:5_post_scale
0100 1:5
5 : 1:6_post_scale
0101 1:6
6 : 1:7_post_scale
0110 1:7
7 : 1:8_post_scale
0111 1:8
8 : 1:9_post_scale
1000 1:9
9 : 1:10_post_scale
1001 1:10
10 : 1:11_post_scale
1010 1:11
11 : 1:12_post_scale
1011 1:12
12 : 1:13_post_scale
1100 1:13
13 : 1:14_post_scale
1101 1:14
14 : 1:15_post_scale
1110 1:15
15 : 1:16_post_scale
1111 1:16
End of enumeration elements list.
RESERVED3 : reserved3
bits : 12 - 43 (32 bit)
access : read-write
Base time period control register for channel1
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_RST_FRM_REG : Time period counter soft reset
bits : 0 - 0 (1 bit)
access : read-write
PWM_TIME_BASE_EN_FRM_REG_CH1 : Base timer enable for channnel1
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
timer is disabled
1 : Enable
timer is enabled
End of enumeration elements list.
PWM_SFT_RST : MC PWM soft reset
bits : 2 - 4 (3 bit)
access : read-write
RESERVED1 : reserved1
bits : 3 - 34 (32 bit)
access : read-write
Base time period status register for channel1
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_DIR_STS_CH1 : Time period counter direction status for channel1.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Downward
downward
1 : Upward
upward
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Time period counter current value for channel1
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_VALUE_CH1 : Time period counter current value for channel1
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Base timer period register of channel2
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_REG_WR_VALUE_CH2 : Value to update the base timer period register of channel 2
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Base time counter initial value register for channal2
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_WR_REG_CH2 : To update the base time counter initial value for channel 2
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Base time period config parameter's register for channel2
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_OPEARATING_MODE_CH2 : Base timer operating mode for channel2
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FREE_RUNNING_MODE
free running mode
1 : SINGLE_EVENT_MODE
single event mode
2 : DOWN_COUNT_MODE
down count mode
3 : NONE1
none1
4 : UP_DOWN_MODE
up/down mode
5 : UP_DOWN_DOUBLER_MODE
up/down mode with interrupts for double PWM updates
6 : NONE2
none2
7 : NONE3
none3
End of enumeration elements list.
RESERVED1 : reserved1
bits : 3 - 6 (4 bit)
access : read-write
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 : Base timer input clock pre scale select value for channel2.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : 1X_CLOCK_PERIOD
1x input clock period
1 : 2X_CLOCK_PERIOD
2x input clock period
2 : 4X_CLOCK_PERIOD
4x input clock period
3 : 16X_CLOCK_PERIOD
16x input clock period
4 : 32X_CLOCK_PERIOD
32x input clock period
5 : NONE1
none1
6 : 64X_CLOCK_PERIOD
64x input clock period
7 : NONE2
none2
End of enumeration elements list.
RESERVED2 : reserved2
bits : 7 - 14 (8 bit)
access : read-write
PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 : Time base output post scale bits for channel2
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : 1:1_POST_SCALE
0000 1:1 post scale
1 : 1:2_POST_SCALE
0001 1:2
2 : 1:3_POST_SCALE
0010 1:3
3 : 1:4_POST_SCALE
0011 1:4
4 : 1:5_POST_SCALE
0100 1:5
5 : 1:6_POST_SCALE
0101 1:6
6 : 1:7_POST_SCALE
0110 1:7
7 : 1:8_POST_SCALE
0111 1:8
8 : 1:9_POST_SCALE
1000 1:9
9 : 1:10_POST_SCALE
1001 1:10
10 : 1:11_POST_SCALE
1010 1:11
11 : 1:12_POST_SCALE
1011 1:12
12 : 1:13_POST_SCALE
1100 1:13
13 : 1:14_POST_SCALE
1101 1:14
14 : 1:15_POST_SCALE
1110 1:15
15 : 1:16_POST_SCALE
1111 1:16
End of enumeration elements list.
RESERVED3 : reserved3
bits : 12 - 43 (32 bit)
access : read-write
Base time period control register for channel2
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_RST_FRM_REG : Time period counter soft reset
bits : 0 - 0 (1 bit)
access : read-write
PWM_TIME_BASE_EN_FRM_REG_CH2 : Base timer enable for channnel2
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
timer is disabled
1 : Enable
timer is enabled
End of enumeration elements list.
PWM_SFT_RST : MC PWM soft reset
bits : 2 - 4 (3 bit)
access : read-write
RESERVED1 : reserved1
bits : 3 - 34 (32 bit)
access : read-write
Base time period status register for channel2
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_DIR_STS_CH2 : Time period counter direction status for channel2.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Downward
downward
1 : Upward
upward
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Time period counter current value register for channel2
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_VALUE_CH2 : Time period counter current value for channel2
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 12 (12 bit)
access : read-only
RESERVED2 : reserved2
bits : 12 - 43 (32 bit)
access : read-only
Base timer period register of channel3
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_REG_WR_VALUE_CH3 : To update the base time counter initial value for channel 3
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Base time counter initial value register for channel3
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_REG_WR_VALUE_CH3 : Value to update the base timer period register of channel 3
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Base time period config parameter's register for channel3
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_OPEARATING_MODE_CH3 : Base timer operating mode for channel3
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FREE_RUNNING_MODE
free running mode
1 : SINGLE_EVENT_MODE
single event mode
2 : DOWN_COUNT_MODE
down count mode
3 : NONE1
none
4 : UP_DOWN_MODE
up/down mode
5 : DOUBLE_PWM_UPDATES
up/down mode with interrupts for double PWM updates
6 : NONE2
none2
7 : NONE3
none3
End of enumeration elements list.
RESERVED1 : reserved1
bits : 3 - 6 (4 bit)
access : read-write
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 : Base timer input clock pre scale select value for channel2.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : 1X_CLOCK_PERIOD
1x input clock period
1 : 2X_CLOCK_PERIOD
2x input clock period
2 : 4X_CLOCK_PERIOD
4x input clock period
3 : 16X_CLOCK_PERIOD
16x input clock period
4 : 32X_CLOCK_PERIOD
32x input clock period
5 : NONE1
none
6 : 64X_CLOCK_PERIOD
64x input clock period
7 : NONE2
none2
End of enumeration elements list.
RESERVED2 : reserved2
bits : 7 - 14 (8 bit)
access : read-write
PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 : Time base output post scale bits for channel3
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : 1:1_POST_SCALE
0000 1:1 post scale
1 : 1:2_POST_SCALE
0001 1:2
2 : 1:3_POST_SCALE
0010 1:3
3 : 1:4_POST_SCALE
0011 1:4
4 : 1:5_POST_SCALE
0100 1:5
5 : 1:6_POST_SCALE
0101 1:6
6 : 1:7_POST_SCALE
0110 1:7
7 : 1:8_POST_SCALE
0111 1:8
8 : 1:9_POST_SCALE
1000 1:9
9 : 1:10_POST_SCALE
1001 1:10
10 : 1:11_POST_SCALE
1010 1:11
11 : 1:12_POST_SCALE
1011 1:12
12 : 1:13_POST_SCALE
1100 1:13
13 : 1:14_POST_SCALE
1101 1:14
14 : 1:15_POST_SCALE
1110 1:15
15 : 1:16_POST_SCALE
1111 1:16
End of enumeration elements list.
RESERVED3 : reserved3
bits : 12 - 43 (32 bit)
access : read-write
Base time period control register for channel3
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_RST_FRM_REG : Time period counter soft reset
bits : 0 - 0 (1 bit)
access : read-write
PWM_TIME_BASE_EN_FRM_REG_CH3 : Base timer enable for channnel3
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
timer is disabled
1 : Enable
timer is enabled
End of enumeration elements list.
PWM_SFT_RST : MC PWM soft reset
bits : 2 - 4 (3 bit)
access : read-write
RESERVED1 : reserved1
bits : 3 - 34 (32 bit)
access : read-write
Base time period status register for channel3
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_DIR_STS_CH3 : Time period counter direction status for channel3.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : downward
downward
1 : upward
upward
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 16 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
Time period counter current value register for channel3
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_VALUE_CH3 : Time period counter current value for channe3
bits : 0 - 15 (16 bit)
access : read-only
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Time period common register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_USE_0TH_TIMER_ONLY : Instead of use four base timers for four channels, use only one base timer for all channels.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ONE_TIMER_ONE_CHANNEL
one base timer for each channel
1 : ONE_TIMER_ALL_CHANNEL
only one base timer for all channels
End of enumeration elements list.
PWM_TIME_PRD_COMMON_TIMER_VALUE : Base timers select to generate special event trigger
bits : 1 - 3 (3 bit)
access : read-write
USE_EXT_TIMER_TRIG_FRM_REG : Enable to use external trigger for base time counter increment or decrement.
bits : 3 - 6 (4 bit)
access : read-write
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-write
Base timer period register of channel 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_REG_WR_VALUE_CH0 : Value to update the base timer period register of channel 0
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Base time counter initial value register for channel 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_WR_REG_CH0 : To update the base time counter initial value for channel 0
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Base time period config parameter's register for channel0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_OPEARATING_MODE_CH0 : Base timer operating mode for channel0
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FREE_RUNNING_MODE
free running mode
1 : SINGLE_EVENT_MODE
single event mode
2 : DOWN_COUNT_MODE
down count mode
3 : NONE1
none1
4 : UP_DOWN_MODE
up/down mode
5 : UP_DOWN_DOUBLER_MODE
up/down mode with interrupts for double PWM updates
6 : NONE2
none2
7 : NONE3
none3
End of enumeration elements list.
RESERVED1 : reserved1
bits : 3 - 6 (4 bit)
access : read-write
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 : Base timer input clock pre scale select value for channel0.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : 1X_CLOCK_PERIOD
1x input clock period
1 : 2X_CLOCK_PERIOD
2x input clock period
2 : 4X_CLOCK_PERIOD
4x input clock period
3 : 16X_CLOCK_PERIOD
16x input clock period
4 : 32X_CLOCK_PERIOD
32x input clock period
5 : NONE1
none1
6 : 64X_CLOCK_PERIOD
64x input clock period
7 : NONE2
none2
End of enumeration elements list.
RESERVED2 : reserved2
bits : 7 - 14 (8 bit)
access : read-write
PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 : Time base output post scale bits for channel0
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : 1:1_POST_SCALE
0000 1 to 1 post scale
1 : 1:2_POST_SCALE
0001 1 to 2
2 : 1:3_POST_SCALE
0010 1 to 3
3 : 1:4_POST_SCALE
0011 1 to 4
4 : 1:5_POST_SCALE
0100 1 to 5
5 : 1:6_POST_SCALE
0101 1 to 6
6 : 1:7_POST_SCALE
0110 1 to 7
7 : 1:8_POST_SCALE
0111 1 to 8
8 : 1:9_POST_SCALE
1000 1 to 9
9 : 1:10_POST_SCALE
1001 1 to 10
10 : 1:11_POST_SCALE
1010 1 to 11
11 : 1:12_POST_SCALE
1011 1:12
12 : 1:13_POST_SCALE
1100 1:13
13 : 1:14_POST_SCALE
1101 1 to 14
14 : 1:15_POST_SCALE
1110 1 to 15
15 : 1:16_POST_SCALE
1111 1 to 16
End of enumeration elements list.
RESERVED3 : reserved3
bits : 12 - 43 (32 bit)
access : read-write
Base time counter initial value register for channel 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_RST_FRM_REG : Time period counter soft reset
bits : 0 - 0 (1 bit)
access : read-write
PWM_TIME_BASE_EN_FRM_REG_CH0 : Base timer enable for channnel0
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
timer is disabled
1 : Enable
timer is enabled
End of enumeration elements list.
PWM_SFT_RST : MC PWM soft reset
bits : 2 - 4 (3 bit)
access : read-write
RESERVED1 : reserved1
bits : 3 - 34 (32 bit)
access : read-only
Base time period status register for channel0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_DIR_STS_CH0 : Time period counter direction status for channel0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Downward
Time period counter direction is downward
1 : Upward
Time period counter direction is upward
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Base Time period counter current value register for channel0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_TIME_PRD_CNTR_VALUE_CH0 : Time period counter current value for channel0
bits : 0 - 15 (16 bit)
access : read-only
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
PWM Interrupt Unmask Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INTR_UNMASK : Interrupt Unmask
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
PWM deadtime for B and channel varies from 0 to 3
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEADTIME_B_CH : Dead time B value to load into deadtime counter B of channel0 to channel3
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : reserved1
bits : 6 - 37 (32 bit)
access : read-write
Duty cycle Control Set Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately
bits : 0 - 3 (4 bit)
access : read-write
DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable. There is a separate bit for each channel
bits : 4 - 11 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Duty cycle Control Reset Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately
bits : 0 - 3 (4 bit)
access : read-write
DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable. There is a separate bit for each channel.
bits : 4 - 11 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Duty cycle Value Register for Channel0 to channel3
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH : Duty cycle value for channel0 to channel3
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Duty cycle Value Register for Channel0 to channel3
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH : Duty cycle value for channel0 to channel3
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Duty cycle Value Register for Channel0 to channel3
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH : Duty cycle value for channel0 to channel3
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Duty cycle Value Register for Channel0 to channel3
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH : Duty cycle value for channel0 to channel3
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Dead time Control Set Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEADTIME_SELECT_ACTIVE : Dead time select bits for PWM going active
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : Disable
means use counter A
1 : Enable
means use counter B
End of enumeration elements list.
DEADTIME_SELECT_INACTIVE : Dead time select bits for PWM going inactive
bits : 4 - 11 (8 bit)
access : read-write
Enumeration:
0 : Disable
means use counter A
1 : Enable
means use counter B
End of enumeration elements list.
DEADTIME_DISABLE_FRM_REG : Dead time counter soft reset for each channel.
bits : 8 - 19 (12 bit)
access : read-write
RESERVED1 : reserved1
bits : 12 - 43 (32 bit)
access : read-only
Dead time Control Reset Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEADTIME_SELECT_ACTIVE : Dead time select bits for PWM going active
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : Disable
means use counter A
1 : Enable
means use counter B
End of enumeration elements list.
DEADTIME_SELECT_INACTIVE : Dead time select bits for PWM going inactive
bits : 4 - 11 (8 bit)
access : read-write
Enumeration:
0 : Disable
means use counter A
1 : Enable
means use counter B
End of enumeration elements list.
DEADTIME_DISABLE_FRM_REG : Dead time counter soft reset for each channel.
bits : 8 - 19 (12 bit)
access : read-write
RESERVED1 : reserved1
bits : 12 - 43 (32 bit)
access : read-only
PWM Interrupt mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INTR_UNMASK : Interrupt Mask
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Dead time Prescale Select Register for A
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEADTIME_PRESCALE_SELECT_A : Dead time prescale selection bits for unit A.
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Dead time Prescale Select Register for B
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEADTIME_PRESCALE_SELECT_B : Dead time prescale selection bits for unit B
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
PWM Interrupt Acknowledgement Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : pwm time period match interrupt for 0th channel will be cleared.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : Disable
No effect.
1 : Enable
PWM time period match interrupt for 0th channel will be cleared.
End of enumeration elements list.
PWM_TIME_PRD_MATCH_INTR_CH0_ACK : pwm time period match interrupt for 0th channel will be cleared
bits : 1 - 2 (2 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm time period match interrupt for 0th channel will be cleared
End of enumeration elements list.
FLT_A_INTR_ACK : pwm fault A interrupt will be cleared.
bits : 2 - 4 (3 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm faultA interrupt will be cleared
End of enumeration elements list.
FLT_B_INTR_ACK : pwm fault B interrupt will be cleared.
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm faultB interrupt will be cleared.
End of enumeration elements list.
RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : pwm time period match interrupt for 1st channel will be cleared
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm time period match interrupt for 1st channel will be cleared
End of enumeration elements list.
PWM_TIME_PRD_MATCH_INTR_CH1_ACK : pwm time period match interrupt for 1st channel will be cleared.
bits : 5 - 10 (6 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm time period match interrupt for 1st channel will be cleared.
End of enumeration elements list.
RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : pwm time period match interrupt for 2nd channel will be cleared.
bits : 6 - 12 (7 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm time period match interrupt for 2nd channel will be cleared
End of enumeration elements list.
PWM_TIME_PRD_MATCH_INTR_CH2_ACK : pwm time period match interrupt for 2nd channel will be cleared.
bits : 7 - 14 (8 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm time period match interrupt for 2nd channel will be cleared.
End of enumeration elements list.
RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : pwm time period match interrupt for 3rd channel will be cleared.
bits : 8 - 16 (9 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm time period match interrupt for 3rd channel will be cleared
End of enumeration elements list.
PWM_TIME_PRD_MATCH_INTR_CH3_ACK : pwm time period match interrupt for 3rd channel will be cleared.
bits : 9 - 18 (10 bit)
access : write-only
Enumeration:
0 : Disable
No effect
1 : Enable
pwm time period match interrupt for 3rd channel will be cleared
End of enumeration elements list.
RESERVED1 : reserved1
bits : 10 - 41 (32 bit)
access : read-write
output override control set register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP_OVERRIDE_SYNC : Output override is synced with pwm time period depending on operating mode
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
output override control reset register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP_OVERRIDE_SYNC : Output override is synced with pwm time period depending on operating mode
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-write
output override enable set register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_OP_OVERRIDE_ENABLE_REG : Pwm output over ride enable
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-write
output override enable reset register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_OP_OVERRIDE_ENABLE_REG : Pwm output over ride enable
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-write
output override value set register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP_OVERRIDE_VALUE : Pwm output over ride value.
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-write
output override enable reset register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP_OVERRIDE_VALUE : Pwm output over ride value.
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-write
fault override control set register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT_A_MODE : Fault A mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
latched mode
1 : Enable
cycle by cycle by mode
End of enumeration elements list.
FLT_B_MODE : Fault B mode
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
latched mode
1 : Enable
cycle by cycle by mode
End of enumeration elements list.
OP_POLARITY_H : Ouput polarity for high (H3, H2, H1, H0) side signals
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
means active low mode
1 : Enable
means active high mode
End of enumeration elements list.
OP_POLARITY_L : Ouput polarity for low (L3, L2, L1, L0) side signals.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
means active low mode
1 : Enable
means active high mode
End of enumeration elements list.
FLT_A_ENABLE : Fault A enable. Separate enable bit is present for channel
bits : 4 - 11 (8 bit)
access : read-write
FLT_B_ENABLE : Fault B enable. Separate enable bit is present for channel
bits : 8 - 19 (12 bit)
access : read-write
COMPLEMENTARY_MODE : PWM I/O pair mode
bits : 12 - 27 (16 bit)
access : read-write
Enumeration:
0 : Disable
PWM I/O pin pair is in the independent output mode
1 : Enable
PWM I/O pin pair is in the complementary output mode
End of enumeration elements list.
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
fault override control reset register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT_A_MODE : Fault B mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
latched mode
1 : Enable
cycle by cycle by mode
End of enumeration elements list.
FLT_B_MODE : Fault B mode
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
latched mode
1 : Enable
cycle by cycle by mode
End of enumeration elements list.
OP_POLARITY_H : Ouput polarity for high (H3, H2, H1, H0) side signals
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
means active low mode
1 : Enable
means active high mode
End of enumeration elements list.
OP_POLARITY_L : Ouput polarity for low (L3, L2, L1, L0) side signals.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
means active low mode
1 : Enable
means active high mode
End of enumeration elements list.
FLT_A_ENABLE : Fault A enable. Separate enable bit is present for channel
bits : 4 - 11 (8 bit)
access : read-write
FLT_B_ENABLE : Fault B enable. Separate enable bit is present for channel
bits : 8 - 19 (12 bit)
access : read-write
COMPLEMENTARY_MODE : PWM I/O pair mode
bits : 12 - 27 (16 bit)
access : read-write
Enumeration:
0 : Disable
PWM I/O pin pair is in the independent output mode
1 : Enable
PWM I/O pin pair is in the complementary output mode
End of enumeration elements list.
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Fault input A PWM override value
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FLT_A_OVERRIDE_VALUE_L0 : 0 bit for L0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_A_OVERRIDE_VALUE_L1 : 1 bit for L1
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_A_OVERRIDE_VALUE_L2 : 2 bit for L2
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_A_OVERRIDE_VALUE_L3 : 3 bit for L3
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_A_OVERRIDE_VALUE_H0 : 4 bit for H0
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_A_OVERRIDE_VALUE_H1 : 5 bit for H1
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_A_OVERRIDE_VALUE_H2 : 6 bit for H2
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_A_OVERRIDE_VALUE_H3 : 7 bit for H3
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-write
Fault input B PWM override value
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FLT_B_OVERRIDE_VALUE_L0 : 0 bit for L0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_B_OVERRIDE_VALUE_L1 : 1 bit for L1
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_B_OVERRIDE_VALUE_L2 : 2 bit for L2
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_B_OVERRIDE_VALUE_L3 : 3 bit for L3
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_B_OVERRIDE_VALUE_H0 : 4 bit for H0
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_B_OVERRIDE_VALUE_H1 : 5 bit for H1
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_B_OVERRIDE_VALUE_H2 : 6 bit for H2
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
PWM_FLT_B_OVERRIDE_VALUE_H3 : 7 bit for H3
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Inactive
0 means PWM output pin is driven inactive on an external fault input A event
1 : Active
1 means PWM output pin is driven active on an external fault input A event.
End of enumeration elements list.
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-write
NONE
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVT_ENABLE_FRM : Special event trigger enable. This is used to enable generation special event trigger
bits : 0 - 0 (1 bit)
access : read-write
SVT_DIRECTION_FRM : Special event trigger for time base direction
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : COUNT_UP
A special event trigger will occur when PWM time base is counting up
1 : COUNT_DOWN
A special event trigger will occur when PWM time base is counting down
End of enumeration elements list.
RESERVED1 : reserved1
bits : 2 - 33 (32 bit)
access : read-write
Special event control reset register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVT_ENABLE_FRM : Special event trigger enable. This is used to enable generation special event trigger
bits : 0 - 0 (1 bit)
access : read-write
SVT_DIRECTION_FRM : Special event trigger for time base direction
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : COUNT_UP
A special event trigger will occur when PWM time base is counting up
1 : COUNT_DOWN
A special event trigger will occur when PWM time base is counting down
End of enumeration elements list.
RESERVED1 : reserved1
bits : 2 - 33 (32 bit)
access : read-write
Special event parameter register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVT_POSTSCALER_SELECT : PWM special event trigger output postscale select bits
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-write
Special event compare value register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_SVT_COMPARE_VALUE : Special event compare value. This is used to compare with pwm time period counter to generate special event trigger
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
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