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UDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x830 byte (0x0)
mem_usage : registers
protection :

Registers

DMA_STATUS

DMA_WAITONREQUEST_STATUS

CHNL_SW_REQUEST

CHNL_USEBURST_SET

CHNL_USEBURST_CLR

CHNL_REQ_MASK_SET

CHNL_REQ_MASK_CLR

CHNL_ENABLE_SET

CHNL_ENABLE_CLR

CHNL_PRI_ALT_SET

CHNL_PRI_ALT_CLR

CHNL_PRIORITY_SET

CHNL_PRIORITY_CLR

DMA_CFG

ERR_CLR

UDMA_SKIP_DESC_FETCH_REG

CTRL_BASE_PTR

UDMA_DONE_STATUS_REG

CHANNEL_STATUS_REG

UDMA_CONFIG_CTRL_REG

UDMA_INTR_MASK_REG

ALT_CTRL_BASE_PTR


DMA_STATUS

UDMA Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DMA_STATUS DMA_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTER_ENABLE RESERVED1 STATE RESERVED2 CHNLS_MINUS1 RESERVED3 TEST_STATUS

MASTER_ENABLE : Enable status of controller
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : Disable

controller is disable

1 : Enable

controller is enable

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 1 - 4 (4 bit)
access : read-only

STATE : Current state of the control state machine
bits : 4 - 11 (8 bit)
access : read-only

RESERVED2 : Reserved2
bits : 8 - 23 (16 bit)
access : read-only

CHNLS_MINUS1 : Number of available DMA channels minus one
bits : 16 - 36 (21 bit)
access : read-only

RESERVED3 : Reserved3
bits : 21 - 48 (28 bit)
access : read-only

TEST_STATUS : To reduce the gate count you can configure the controller
bits : 28 - 59 (32 bit)
access : read-only

Enumeration:

0 : 0x0

Controller does not includes integration test logic

1 : 0x1

Controller does not includes integration test logic

End of enumeration elements list.


DMA_WAITONREQUEST_STATUS

Channel Wait on request status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DMA_WAITONREQUEST_STATUS DMA_WAITONREQUEST_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_WAITONREQ_STATUS

DMA_WAITONREQ_STATUS : Per Channel wait on request status
bits : 0 - 31 (32 bit)
access : read-only


CHNL_SW_REQUEST

Channel Software Request
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CHNL_SW_REQUEST CHNL_SW_REQUEST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_SW_REQUEST

CHNL_SW_REQUEST : Set the appropriate bit to generate a software DMA request on the corresponding DMA channel
bits : 0 - 31 (32 bit)
access : write-only


CHNL_USEBURST_SET

UDMA Channel use burst set
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNL_USEBURST_SET CHNL_USEBURST_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_USEBURST_SET

CHNL_USEBURST_SET : The use burst status, or disables dma_sreq[C] from generating DMA requests.
bits : 0 - 31 (32 bit)
access : read-write


CHNL_USEBURST_CLR

UDMA Channel use burst clear
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CHNL_USEBURST_CLR CHNL_USEBURST_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_USEBURST_CLR

CHNL_USEBURST_CLR : Set the appropriate bit to enable dma_sreq[] to generate requests
bits : 0 - 31 (32 bit)
access : write-only


CHNL_REQ_MASK_SET

UDMA Channel request mask set Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNL_REQ_MASK_SET CHNL_REQ_MASK_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_REQ_MASK_SET

CHNL_REQ_MASK_SET : Returns the request mask status of dma_req[] and dma_sreq[], or disables the corresponding channel from generating DMA requests
bits : 0 - 31 (32 bit)
access : read-write


CHNL_REQ_MASK_CLR

UDMA Channel request mask clear
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CHNL_REQ_MASK_CLR CHNL_REQ_MASK_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_REQ_MASK_CLR

CHNL_REQ_MASK_CLR : Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[] and dma_sreq[]
bits : 0 - 31 (32 bit)
access : write-only


CHNL_ENABLE_SET

UDMA Channel enable register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNL_ENABLE_SET CHNL_ENABLE_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE_SET

CHNL_ENABLE_SET : This Bits are Used to Load the 16bits of Source address
bits : 0 - 31 (32 bit)
access : read-write


CHNL_ENABLE_CLR

UDMA Channel enable clear register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CHNL_ENABLE_CLR CHNL_ENABLE_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE_CLR

CHNL_ENABLE_CLR : Set the appropriate bit to disable the corresponding DMA channel
bits : 0 - 31 (32 bit)
access : write-only


CHNL_PRI_ALT_SET

UDMA Channel primary or alternate set
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNL_PRI_ALT_SET CHNL_PRI_ALT_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRI_ALT_SET

CHNL_PRI_ALT_SET : Returns the channel control data structure status or selects the alternate data structure for the corresponding DMA channel
bits : 0 - 31 (32 bit)
access : read-write


CHNL_PRI_ALT_CLR

UDMA Channel primary alternate clear
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CHNL_PRI_ALT_CLR CHNL_PRI_ALT_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRI_ALT_CLR

CHNL_PRI_ALT_CLR : Set the appropriate bit to select the primary data structure for the corresponding DMA channel
bits : 0 - 31 (32 bit)
access : write-only


CHNL_PRIORITY_SET

UDMA Channel Priority Set
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNL_PRIORITY_SET CHNL_PRIORITY_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRIORITY_SET

CHNL_PRIORITY_SET : Set the appropriate bit to select the primary data structure for the corresponding DMA channel
bits : 0 - 31 (32 bit)
access : read-write


CHNL_PRIORITY_CLR

UDMA Channel Priority Clear
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CHNL_PRIORITY_CLR CHNL_PRIORITY_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_PRIORITY_CLR

CHNL_PRIORITY_CLR : Set the appropriate bit to select the default priority level for the specified DMA channel
bits : 0 - 31 (32 bit)
access : write-only


DMA_CFG

DMA Configuration
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DMA_CFG DMA_CFG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTER_ENABLE RESERVED1 CHNL_PROT_CTRL RESERVED2

MASTER_ENABLE : Enable for the controller
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : Disable

controller is disable

1 : Enable

controller is enable

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 1 - 5 (5 bit)
access : write-only

CHNL_PROT_CTRL : Sets the AHB-Lite protection by controlling the HPROT[3:1]] signal levels as follows Bit[7]-Controls HPROT[3] to indicate if cacheable access is occurring Bit[6]-Controls HPROT[2] to indicate if cacheable access is occurring Bit[5]-Controls HPROT[1] to indicate if cacheable access is occurring
bits : 5 - 12 (8 bit)
access : write-only

RESERVED2 : Reserved2
bits : 8 - 39 (32 bit)
access : write-only


ERR_CLR

UDMA Bus Error Clear Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERR_CLR ERR_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_CLR RESERVED1

ERR_CLR : Returns the status of dma_err
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disabled

Read as:0 = dma_err is LOW Write as:0 = No effect, status of dma_err is unchanged

1 : enabled

Read as:1 = dma_err is HIGH Write as:1 = Sets dma_err LOW

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 1 - 32 (32 bit)
access : read-write


UDMA_SKIP_DESC_FETCH_REG

UDMA skip descriptor fetch Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMA_SKIP_DESC_FETCH_REG UDMA_SKIP_DESC_FETCH_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SKIP_DESC_FETCH

SKIP_DESC_FETCH : improving the performance of transfer and saves bus cycles. This features has to be enabled always.
bits : 0 - 31 (32 bit)
access : read-write


CTRL_BASE_PTR

Channel Control Data Base Pointer
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_BASE_PTR CTRL_BASE_PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED1 CTRL_BASE_PTR

RESERVED1 : Reserved1
bits : 0 - 9 (10 bit)
access : write-only

CTRL_BASE_PTR : Pointer to the base address of the primary data structure
bits : 10 - 41 (32 bit)
access : read-write


UDMA_DONE_STATUS_REG

UDMA Done status Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMA_DONE_STATUS_REG UDMA_DONE_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE_STATUS_CHANNEL_0 DONE_STATUS_CHANNEL_1 DONE_STATUS_CHANNEL_2 DONE_STATUS_CHANNEL_3 DONE_STATUS_CHANNEL_4 DONE_STATUS_CHANNEL_5 DONE_STATUS_CHANNEL_6 DONE_STATUS_CHANNEL_7 DONE_STATUS_CHANNEL_8 DONE_STATUS_CHANNEL_9 DONE_STATUS_CHANNEL_10 DONE_STATUS_CHANNEL_11 DONE_STATUS_CHANNEL_12 DONE_STATUS_CHANNEL_13 DONE_STATUS_CHANNEL_14 DONE_STATUS_CHANNEL_15 DONE_STATUS_CHANNEL_16 DONE_STATUS_CHANNEL_17 DONE_STATUS_CHANNEL_18 DONE_STATUS_CHANNEL_19 DONE_STATUS_CHANNEL_20 DONE_STATUS_CHANNEL_21 DONE_STATUS_CHANNEL_22 DONE_STATUS_CHANNEL_23 DONE_STATUS_CHANNEL_24 DONE_STATUS_CHANNEL_25 DONE_STATUS_CHANNEL_26 DONE_STATUS_CHANNEL_27 DONE_STATUS_CHANNEL_28 DONE_STATUS_CHANNEL_29 DONE_STATUS_CHANNEL_30 DONE_STATUS_CHANNEL_31

DONE_STATUS_CHANNEL_0 : UDMA done Status of the channel 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 0th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_1 : UDMA done Status of the channel 1
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 1st Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_2 : UDMA done Status of the channel 2
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 2nd Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_3 : UDMA done Status of the channel 3
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 3rd Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_4 : UDMA done Status of the channel 4
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 4th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_5 : UDMA done Status of the channel 5
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 5th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_6 : UDMA done Status of the channel 6
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 6th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_7 : UDMA done Status of the channel 7
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 7th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_8 : UDMA done Status of the channel 8
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 8th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_9 : UDMA done Status of the channel 9
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 9th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_10 : UDMA done Status of the channel 10
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 10th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_11 : UDMA done Status of the channel 3
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 11th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_12 : UDMA done Status of the channel 12
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 12th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_13 : UDMA done Status of the channel 13
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 13th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_14 : UDMA done Status of the channel 14
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 14th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_15 : UDMA done Status of the channel 15
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 15th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_16 : UDMA done Status of the channel 16
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 16th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_17 : UDMA done Status of the channel 17
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 17th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_18 : UDMA done Status of the channel 18
bits : 18 - 36 (19 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 18th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_19 : UDMA done Status of the channel 19
bits : 19 - 38 (20 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 19th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_20 : UDMA done Status of the channel 3
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 20th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_21 : UDMA done Status of the channel 21
bits : 21 - 42 (22 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 21th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_22 : UDMA done Status of the channel 22
bits : 22 - 44 (23 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 22th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_23 : UDMA done Status of the channel 23
bits : 23 - 46 (24 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 23rd Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_24 : UDMA done Status of the channel 24
bits : 24 - 48 (25 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 24th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_25 : UDMA done Status of the channel 25
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 25th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_26 : UDMA done Status of the channel 26
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 26th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_27 : UDMA done Status of the channel 27
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 27th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_28 : UDMA done Status of the channel 28
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 28th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_29 : UDMA done Status of the channel 29
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 29th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_30 : UDMA done Status of the channel 30
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 30th Write as:1 will clear the bit

End of enumeration elements list.

DONE_STATUS_CHANNEL_31 : UDMA done Status of the channel 31
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : disabled

Write as:0 will have no effect

1 : enabled

Read as:1 indicates the transfer is completed for channel 31st Write as:1 will clear the bit

End of enumeration elements list.


CHANNEL_STATUS_REG

Channel status Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL_STATUS_REG CHANNEL_STATUS_REG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY_OR_IDEAL_STATUS_CHANNEL_0 BUSY_OR_IDEAL_STATUS_CHANNEL_1 BUSY_OR_IDEAL_STATUS_CHANNEL_2 BUSY_OR_IDEAL_STATUS_CHANNEL_3 BUSY_OR_IDEAL_STATUS_CHANNEL_4 BUSY_OR_IDEAL_STATUS_CHANNEL_5 BUSY_OR_IDEAL_STATUS_CHANNEL_6 BUSY_OR_IDEAL_STATUS_CHANNEL_7 BUSY_OR_IDEAL_STATUS_CHANNEL_8 BUSY_OR_IDEAL_STATUS_CHANNEL_9 BUSY_OR_IDEAL_STATUS_CHANNEL_10 BUSY_OR_IDEAL_STATUS_CHANNEL_11 BUSY_OR_IDEAL_STATUS_CHANNEL_12 BUSY_OR_IDEAL_STATUS_CHANNEL_13 BUSY_OR_IDEAL_STATUS_CHANNEL_14 BUSY_OR_IDEAL_STATUS_CHANNEL_15 BUSY_OR_IDEAL_STATUS_CHANNEL_16 BUSY_OR_IDEAL_STATUS_CHANNEL_17 BUSY_OR_IDEAL_STATUS_CHANNEL_18 BUSY_OR_IDEAL_STATUS_CHANNEL_19 BUSY_OR_IDEAL_STATUS_CHANNEL_20 BUSY_OR_IDEAL_STATUS_CHANNEL_21 BUSY_OR_IDEAL_STATUS_CHANNEL_22 BUSY_OR_IDEAL_STATUS_CHANNEL_23 BUSY_OR_IDEAL_STATUS_CHANNEL_24 BUSY_OR_IDEAL_STATUS_CHANNEL_25 BUSY_OR_IDEAL_STATUS_CHANNEL_26 BUSY_OR_IDEAL_STATUS_CHANNEL_27 BUSY_OR_IDEAL_STATUS_CHANNEL_28 BUSY_OR_IDEAL_STATUS_CHANNEL_29 BUSY_OR_IDEAL_STATUS_CHANNEL_30 BUSY_OR_IDEAL_STATUS_CHANNEL_31

BUSY_OR_IDEAL_STATUS_CHANNEL_0 : Reading 1 indicates that the channel 0 is busy
bits : 0 - 0 (1 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_1 : Reading 1 indicates that the channel 1 is busy
bits : 1 - 2 (2 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_2 : Reading 1 indicates that the channel 2 is busy
bits : 2 - 4 (3 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_3 : Reading 1 indicates that the channel 3 is busy
bits : 3 - 6 (4 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_4 : Reading 1 indicates that the channel 4 is busy
bits : 4 - 8 (5 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_5 : Reading 1 indicates that the channel 5 is busy
bits : 5 - 10 (6 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_6 : Reading 1 indicates that the channel 6 is busy
bits : 6 - 12 (7 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_7 : Reading 1 indicates that the channel 7 is busy
bits : 7 - 14 (8 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_8 : Reading 1 indicates that the channel 8 is busy
bits : 8 - 16 (9 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_9 : Reading 1 indicates that the channel 9 is busy
bits : 9 - 18 (10 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_10 : Reading 1 indicates that the channel 10 is busy
bits : 10 - 20 (11 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_11 : Reading 1 indicates that the channel 11 is busy
bits : 11 - 22 (12 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_12 : Reading 1 indicates that the channel 12 is busy
bits : 12 - 24 (13 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_13 : Reading 1 indicates that the channel 13 is busy
bits : 13 - 26 (14 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_14 : Reading 1 indicates that the channel 14 is busy
bits : 14 - 28 (15 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_15 : Reading 1 indicates that the channel 15 is busy
bits : 15 - 30 (16 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_16 : Reading 1 indicates that the channel 16 is busy
bits : 16 - 32 (17 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_17 : Reading 1 indicates that the channel 17 is busy
bits : 17 - 34 (18 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_18 : Reading 1 indicates that the channel 18 is busy
bits : 18 - 36 (19 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_19 : Reading 1 indicates that the channel 19 is busy
bits : 19 - 38 (20 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_20 : Reading 1 indicates that the channel 20 is busy
bits : 20 - 40 (21 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_21 : Reading 1 indicates that the channel 21 is busy
bits : 21 - 42 (22 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_22 : Reading 1 indicates that the channel 22 is busy
bits : 22 - 44 (23 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_23 : Reading 1 indicates that the channel 23 is busy
bits : 23 - 46 (24 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_24 : Reading 1 indicates that the channel 24 is busy
bits : 24 - 48 (25 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_25 : Reading 1 indicates that the channel 25 is busy
bits : 25 - 50 (26 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_26 : Reading 1 indicates that the channel 26 is busy
bits : 26 - 52 (27 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_27 : Reading 1 indicates that the channel 27 is busy
bits : 27 - 54 (28 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_28 : Reading 1 indicates that the channel 28 is busy
bits : 28 - 56 (29 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_29 : Reading 1 indicates that the channel 29 is busy
bits : 29 - 58 (30 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_30 : Reading 1 indicates that the channel 30 is busy
bits : 30 - 60 (31 bit)
access : read-only

BUSY_OR_IDEAL_STATUS_CHANNEL_31 : Reading 1 indicates that the channel 31 is busy
bits : 31 - 62 (32 bit)
access : read-only


UDMA_CONFIG_CTRL_REG

DMA Controller Transfer Length Register
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMA_CONFIG_CTRL_REG UDMA_CONFIG_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SINGLE_REQUEST_ENABLE RESERVED1

SINGLE_REQUEST_ENABLE : Enabled signal for single request
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disabled

Single request will be disabled

1 : enabled

Single request will be enabled

End of enumeration elements list.

RESERVED1 : Reserved for future use.
bits : 1 - 32 (32 bit)
access : read-write


UDMA_INTR_MASK_REG

Mask the uDMA interrupt register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UDMA_INTR_MASK_REG UDMA_INTR_MASK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_INTR_MASK RESERVED1

UDMA_INTR_MASK : Mask the uDMA interrupt register
bits : 0 - 11 (12 bit)
access : read-write

RESERVED1 : RESERVED1
bits : 12 - 43 (32 bit)
access : read-only


ALT_CTRL_BASE_PTR

Channel Alternate Control Data Base Pointer
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

ALT_CTRL_BASE_PTR ALT_CTRL_BASE_PTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALT_CTRL_BASE_PTR

ALT_CTRL_BASE_PTR : Base address of the alternative data structure
bits : 0 - 31 (32 bit)
access : read-only



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