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TIMERS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection :

Registers

MCUULP_TMR_MATCH

MCUULP_TMR_CNTRL

MCUULP_TMR_INTR_STAT

MCUULP_TMR_US_PERIOD_INT

MCUULP_TMR_US_PERIOD_FRAC

MCUULP_TMR_MS_PERIOD_INT

MCUULP_TMR_MS_PERIOD_FRAC

MCUULP_TMR_ACTIVE_STATUS


MCUULP_TMR_MATCH

Timer Match Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_MATCH MCUULP_TMR_MATCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_MATCH

TMR_MATCH : This bits are used to program the lower significant 16-bits of timer time out value in millisecond or number of system clocks
bits : 0 - 31 (32 bit)
access : read-write


MCUULP_TMR_CNTRL

Timer Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_CNTRL MCUULP_TMR_CNTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_START TMR_INTR_CLR TMR_INTR_ENABLE TMR_TYPE TMR_MODE TMR_STOP COUNTER_UP RESERVED1

TMR_START : This Bit are Used to start the timer timer gets reset upon setting this bit
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

1 : None

Timer start

End of enumeration elements list.

TMR_INTR_CLR : This Bit are Used to clear the timer
bits : 1 - 2 (2 bit)
access : write-only

Enumeration:

1 : Clear_Interrupt

Clear interrupt

End of enumeration elements list.

TMR_INTR_ENABLE : This Bit are Used to enable the time out interrupt
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : Enable

Interrupt enable

0 : Disable

Interrupt disable

End of enumeration elements list.

TMR_TYPE : This Bit are Used to select the type of timer
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

2 : 256_MICRO_SECOND

256 Micro second mode

1 : ONE_MICRO_SECOND

1 Micro second mode

0 : COUNT_DOWN_TIMER

Count down timer

End of enumeration elements list.

TMR_MODE : This Bit are Used to select the mode working of timer
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : Enable

Periodic timer

0 : Disable

One shot timer

End of enumeration elements list.

TMR_STOP : This Bit are Used to stop the timer
bits : 6 - 12 (7 bit)
access : write-only

Enumeration:

1 : None

Stops the timer

End of enumeration elements list.

COUNTER_UP : For reading/tracking counter in up counting this bit has to be set
bits : 7 - 14 (8 bit)
access : read-write

RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-write


MCUULP_TMR_INTR_STAT

Timer Status Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_INTR_STAT MCUULP_TMR_INTR_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR0_INTR_STATUS TMR1_INTR_STATUS TMR2_INTR_STATUS TMR3_INTR_STATUS RESERVED1

TMR0_INTR_STATUS : This bit indicates status of the interrupt generated by timer 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : Interrupt_Present

Interrupt present

0 : Interrupt_Absent

No Interrupt present

End of enumeration elements list.

TMR1_INTR_STATUS : This bit indicates status of the interrupt generated by timer 1
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : Interrupt_Present

Interrupt present

0 : Interrupt_Absent

No Interrupt present

End of enumeration elements list.

TMR2_INTR_STATUS : This bit indicates status of the interrupt generated by timer 2
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : Interrupt_Present

Interrupt present

0 : Interrupt_Absent

No Interrupt present

End of enumeration elements list.

TMR3_INTR_STATUS : This bit indicates status of the interrupt generated by timer 3
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : Interrupt_Present

Interrupt present

0 : Interrupt_Absent

No Interrupt present

End of enumeration elements list.

RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only


MCUULP_TMR_US_PERIOD_INT

Timer micro second period Integral Part Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_US_PERIOD_INT MCUULP_TMR_US_PERIOD_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_US_PERIOD_INT RESERVED1

TMR_US_PERIOD_INT : This bits are used to program the integer part of number of clock cycles per microseconds of the system clock used
bits : 0 - 15 (16 bit)
access : read-write

RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only


MCUULP_TMR_US_PERIOD_FRAC

Timer microsecond period Fractional Part Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_US_PERIOD_FRAC MCUULP_TMR_US_PERIOD_FRAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_US_PERIOD_FRAC RESERVED1

TMR_US_PERIOD_FRAC : This bits are used to program the fractional part of number of clock cycles per microseconds of the system clock used
bits : 0 - 7 (8 bit)
access : read-write

RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only


MCUULP_TMR_MS_PERIOD_INT

Timer 256 microsecond period Integral Part Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_MS_PERIOD_INT MCUULP_TMR_MS_PERIOD_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_MS_PERIOD_INT RESERVED1

TMR_MS_PERIOD_INT : This bits are used to program the integer part of number of clock cycles per 256 microseconds of the system clock used
bits : 0 - 15 (16 bit)
access : read-write

RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only


MCUULP_TMR_MS_PERIOD_FRAC

Timer 256 microsecond period Fractional Part Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_MS_PERIOD_FRAC MCUULP_TMR_MS_PERIOD_FRAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_MS_PERIOD_FRAC RESERVED1

TMR_MS_PERIOD_FRAC : This bits are used to program the fractional part of number of clock cycles per 256 microseconds of the system clock used
bits : 0 - 7 (8 bit)
access : read-write

RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only


MCUULP_TMR_ACTIVE_STATUS

Timer Active Status Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MCUULP_TMR_ACTIVE_STATUS MCUULP_TMR_ACTIVE_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER_ACTIVE RESERVED1

TIMER_ACTIVE : Timer active status for each timer. LSB bit specifies the status for 0th timer and so on.
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

1 : Timer_Active

Interrupt present

0 : Timer_Inative

No Interrupt present

End of enumeration elements list.

RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only



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