GEN_CTRL_SET_REG

POLYNOMIAL_CTRL_SET

POLYNOMIAL_CTRL_RESET

LFSR_INIT_VAL

LFSR_INIT_CTRL_SET

LFSR_INIT_CTRL_RESET

DIN_FIFO

DIN_CTRL_SET

DIN_CTRL_RESET_REG

DIN_NUM_BYTES

DIN_STS

LFSR_STATE

GEN_CTRL_RESET

GEN_STS

POLYNOMIAL

SOFT_RST : Soft reset. This clears the FIFO and settles all the state machines to their IDLE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use.
bits : 1 - 32 (32 bit)
access : read-write

POLYNOMIAL_WIDTH_SET : Polynomial width set. Number of bits/width of the polynomial has to be written here for the computation of final CRC. If a new width has to be configured, clear the existing length first by writing 0x1f in polynomial_ctrl_reset register. When read, actual polynomial width is read.
bits : 0 - 4 (5 bit)
access : read-write

RESERVED1 : Reserved for future use.
bits : 5 - 36 (32 bit)
access : read-write

POLYNOMIAL_WIDTH_SET : Polynomial width reset. If a new width has to be configured, clear the existing length first by writing 0x1f. When read, actual polynomial width is read.
bits : 0 - 4 (5 bit)
access : read-write

RESERVED1 : Reserved for future use.
bits : 5 - 36 (32 bit)
access : read-write

LFSR_INIT : This holds LFSR initialization value. When ever LFSR needs to be initialized, this has to be updated with the init value and trigger init_lfsr in LFSR_INIT_CTRL_SET register. For example, in WiFi case, 0xffffffff is used as init value of LFSR.
bits : 0 - 31 (32 bit)
access : read-write

CLEAR_LFSR : Clear LFSR state. When this is set, LFSR state is cleared to 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INIT_LFSR : Initialize LFSR state. When this is set LFSR state will be initialized with LFSR_INIT_VAL/bit swapped LFSR_INIT_VAL in the next cycle
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_SWAPPED_INIT_VAL : Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use.
bits : 3 - 34 (32 bit)
access : read-write

RESERVED1 : Reserved for future use.
bits : 0 - 0 (1 bit)
access : read-write

RESERVED2 : Reserved for future use.
bits : 1 - 2 (2 bit)
access : read-write

USE_SWAPPED_INIT_VAL : Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED3 : Reserved for future use.
bits : 3 - 34 (32 bit)
access : read-write

DIN_FIFO : FIFO input port is mapped to this register. Data on which the final CRC has to be computed has to be loaded to this FIFO
bits : 0 - 31 (32 bit)
access : write-only

DIN_WIDTH_REG : Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits.
bits : 0 - 4 (5 bit)
access : read-write

DIN_WIDTH_FROM_REG : Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIN_WIDTH_FROM_CNT : Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length and number of bytes remaining will form the valid bits (which ever is less that will be considered as valid bits).
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_SWAPPED_DIN : Use bit swapped input data. If this is set, input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET_FIFO_PTRS : Reset fifo pointer. This clears the FIFO.When this is set, FIFO will be cleared.
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use.
bits : 9 - 32 (24 bit)
access : read-write

FIFO_AEMPTY_THRESHOLD : FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value.
bits : 24 - 51 (28 bit)
access : read-write

FIFO_AFULL_THRESHOULD : FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value
bits : 28 - 59 (32 bit)
access : read-write

DIN_WIDTH_REG : Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits.
bits : 0 - 4 (5 bit)
access : read-write

DIN_WIDTH_FROM_REG : Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIN_WIDTH_FROM_CNT : Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length and number of bytes remaining will form the valid bits (which ever is less that will be considered as valid bits).
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_SWAPPED_DIN : Use bit swapped input data. If this is set input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use.
bits : 8 - 16 (9 bit)
access : read-write

RESERVED2 : Reserved for future use.
bits : 9 - 32 (24 bit)
access : read-write

FIFO_AEMPTY_THRESHOLD : FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value.
bits : 24 - 51 (28 bit)
access : read-write

FIFO_AFULL_THRESHOULD : FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value
bits : 28 - 59 (32 bit)
access : read-write

DIN_NUM_BYTES : in out data number of bytes
bits : 0 - 31 (32 bit)
access : read-write

FIFO_EMPTY : FIFO empty indication status
bits : 0 - 0 (1 bit)
access : read-only

FIFO_AEMPTY : FIFO almost empty indication status.
bits : 1 - 2 (2 bit)
access : read-only

FIFO_AFULL : FIFO almost full indication status
bits : 2 - 4 (3 bit)
access : read-only

FIFO_FULL : FIFO full indication status
bits : 3 - 6 (4 bit)
access : read-only

FIFO_OCC : FIFO occupancy
bits : 4 - 13 (10 bit)
access : read-only

RESERVED1 : Reserved for future use.
bits : 10 - 41 (32 bit)
access : read-only

LFSR_STATE : If LFSR dynamic loading is required this can be used for writing the LFSR state directly.
bits : 0 - 31 (32 bit)
access : read-write

RESERVED1 : Reserved for future use.
bits : 0 - 31 (32 bit)
access : read-write

CALC_DONE : When the computation of final CRC with the data out of fifo, this will get set to 1 otherwise 0
bits : 0 - 0 (1 bit)
access : read-only

DIN_NUM_BYTES_DONE : When number of bytes requested for computation of final CRC is read from fifo by internal FSM, this will get set to 1 otherwise 0.
bits : 1 - 2 (2 bit)
access : read-only

RESERVED1 : Reserved for future use.
bits : 2 - 33 (32 bit)
access : read-only

POLYNOMIAL : Polynomial register. This register holds the polynomial with which the final CRC is computed.When write Polynomial will be updated.When read read polynomial.
bits : 0 - 31 (32 bit)
access : read-write