\n
address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection :
Direct Access Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR_BITS : These bits specifies the address to write or read from EFUSE macro model
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-write
Read address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ADDR_BITS : These bits specifies the address from which read operation has to be performed
bits : 0 - 12 (13 bit)
access : read-write
RESERVED1 : reserved1
bits : 13 - 27 (15 bit)
access : read-only
DO_READ : Enables read FSM after EFUSE is enabled
bits : 15 - 30 (16 bit)
access : write-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
Read address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_DATA_BITS : These bits specifies the data bits that are read from a given address specified in the EFUSE_READ_ADDRESS_REGISTER bits 8:0
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 22 (15 bit)
access : read-only
READ_FSM_DONE : Indicates read fsm is done. After this read data is available in EFUSE_READ_DATA_REGISTER bits 7:0
bits : 15 - 30 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
Read address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFUSE_ENABLED : This bit specifies whether the EFUSE is enabled or not
bits : 0 - 0 (1 bit)
access : read-only
RESERVED1 : reserved1
bits : 1 - 2 (2 bit)
access : read-only
EFUSE_DOUT_SYNC : This bit specifies the 8-bit data read out from the EFUSE macro. This is synchronized with pclk
bits : 2 - 11 (10 bit)
access : read-only
RESERVED2 : reserved2
bits : 10 - 25 (16 bit)
access : read-only
RESERVED3 : reserved3
bits : 16 - 47 (32 bit)
access : read-only
none
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSUR_CS : CSB to STROBE setup time into read mode
bits : 0 - 3 (4 bit)
access : read-write
TSQ : Q7-Q0 access time from STROBE rising edge
bits : 4 - 11 (8 bit)
access : read-write
THRA : for 32x8 macro: A4 A0 to STROBE hold time into Read mode 5122x8 macro: A8 A0 to STROBE hold time into Read mode
bits : 8 - 19 (12 bit)
access : read-write
RESERVED1 : reserved1
bits : 12 - 27 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
none
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFUSE_MEM_MAP_LEN : 0: 8 bit read 1: 16 bit read
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 16 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFUSE_READ_BLOCK_STARTING_LOCATION : Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFUSE_READ_BLOCK_END_LOCATION : End address till which the read has to be blocked. Once the end address is written , it cannot be changed till power on reset is given.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
The Transmit Poll Demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
efuse_read_block_enable : Enable for blocking the read access from a programmable memory location
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 16 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
none
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFUSE_STROBE_CLR_CNT : Strobe signal Clear count in direct access mode. value depends on APB clock frequency of eFuse controller
bits : 0 - 8 (9 bit)
access : read-write
EFUSE_STROBE_ENABLE : none
bits : 9 - 18 (10 bit)
access : read-write
RESERVED1 : reserved1
bits : 10 - 25 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
Direct Access Set Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGENB : Set Program enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
Sets EFUSE program enable (PGENB) pin when direct accessing is enabled
0 : disable
no effect
End of enumeration elements list.
CSB : Set Chip Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
Sets EFUSE Chip enable (CSB) pin when direct accessing is enabled
0 : disable
no effect
End of enumeration elements list.
STROBE : Set strobe enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : enable
Sets EFUSE STROBE enable (STROBE) pin when direct accessing is enabled
0 : disable
no effect
End of enumeration elements list.
LOAD : Set Load enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : enable
Sets EFUSE load enable (LOAD) pin when direct accessing is enabled
0 : disable
no effect
End of enumeration elements list.
RESERVED1 : reserved1
bits : 4 - 19 (16 bit)
access : read-write
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-write
Direct Access Clear Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGENB : Clear Program enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
Clear EFUSE program enable (PGENB) pin when direct accessing is enabled
0 : disable
no effect
End of enumeration elements list.
CSB : Clear Chip Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
Clear EFUSE Chip enable (CSB) pin when direct accessing is enabled
0 : disable
no effect
End of enumeration elements list.
RESERVED1 : reserved1
bits : 2 - 4 (3 bit)
access : read-only
LOAD : Clear Load enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : enable
Clear EFUSE load enable (LOAD) pin when direct accessing is enabled
0 : disable
no effect
End of enumeration elements list.
RESERVED2 : reserved2
bits : 4 - 19 (16 bit)
access : read-only
RESERVED3 : reserved3
bits : 16 - 47 (32 bit)
access : read-only
Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFUSE_ENABLE : This bit specifies whether the EFUSE module is enabled or not
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
EFUSE module enabled
0 : disable
EFUSE module disabled
End of enumeration elements list.
EFUSE_DIRECT_PATH_ENABLE : This bit specifies whether the EFUSE direct path is enabled or not for direct accessing of the EFUSE pins
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : enable
EFUSE direct accessing enabled
0 : disable
EFUSE direct accessing disabled
End of enumeration elements list.
ENABLE_EFUSE_WRITE : Controls the switch on VDDIQ for eFuse read/write.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : enable
VDDIQ is supplied
0 : disable
VDDIQ is gated
End of enumeration elements list.
RESERVED1 : reserved1
bits : 3 - 18 (16 bit)
access : read-only
RESERVED2 : reserved2
bits : 16 - 47 (32 bit)
access : read-only
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