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CCI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20C byte (0x0)
mem_usage : registers
protection :

Registers

CONTROL

MSB_A_S1

MSB_A_S2

FIFO_THRESHOLD_REG

TRANS_ADDRESS

PREFETCH_CTRL

MODE_INTR_STATUS

LSB_A_S1

LSB_A_S2


CONTROL

CCI control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_SLAVES ENABLED_SLAVES EBT_S ADDR_WIDTH_CONFIG TRANSLATE_ENABLE MODE RESERVED1 SLAVE_PRIORITY TIME_OUT_PRG RESERVED2 DISABLE_TIME_OUT_FOR_DATA_ACCESS SELECT_TIME_OUT_INTR_OR_MSG_INTR CCI_CTRL_ENABLE

NUM_SLAVES : Indicates the number of slaves
bits : 0 - 1 (2 bit)
access : read-write

ENABLED_SLAVES : Indicates Slaves enable.
bits : 2 - 6 (5 bit)
access : read-write

EBT_S : Support for Early Burst Termination
bits : 5 - 10 (6 bit)
access : read-write

ADDR_WIDTH_CONFIG : address width configuration of AHB slave during address phase
bits : 6 - 13 (8 bit)
access : read-write

TRANSLATE_ENABLE : translation enable
bits : 8 - 16 (9 bit)
access : read-write

MODE : This bit represents mode of the interface
bits : 9 - 20 (12 bit)
access : read-write

RESERVED1 : reserved1
bits : 12 - 24 (13 bit)
access : read-write

SLAVE_PRIORITY : This bits will represents priority of the slaves
bits : 13 - 28 (16 bit)
access : read-write

TIME_OUT_PRG : configurable time out value for slave response.
bits : 16 - 41 (26 bit)
access : read-write

RESERVED2 : reserved2
bits : 26 - 54 (29 bit)
access : read-write

DISABLE_TIME_OUT_FOR_DATA_ACCESS : configurable time out value for slave response.
bits : 29 - 58 (30 bit)
access : read-write

SELECT_TIME_OUT_INTR_OR_MSG_INTR : configurable time out value for slave response.
bits : 30 - 60 (31 bit)
access : read-write

CCI_CTRL_ENABLE : configurable time out value for slave response.
bits : 31 - 62 (32 bit)
access : read-write


MSB_A_S1

upper Address of slave 0 supported
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSB_A_S1 MSB_A_S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIGHER_ADDRESS

HIGHER_ADDRESS : Higher Address of slave 0 supported. Make sure that slave0 is enabled.
bits : 0 - 31 (32 bit)
access : read-write


MSB_A_S2

UPPER Address of slave 0 supported
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSB_A_S2 MSB_A_S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIGHER_ADDRESS

HIGHER_ADDRESS : Higher Address of slave 1 supported. Make sure that slave1 is enabled.
bits : 0 - 31 (32 bit)
access : read-write


FIFO_THRESHOLD_REG

CCI fifo threshold
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_THRESHOLD_REG FIFO_THRESHOLD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_AFULL_THRESHOLD FIFO_AEMPTY_THRESHOLD RESERVED1

FIFO_AFULL_THRESHOLD : ALMOST full threshold
bits : 0 - 4 (5 bit)
access : read-write

FIFO_AEMPTY_THRESHOLD : ALMOST empty threshold
bits : 5 - 14 (10 bit)
access : read-write

RESERVED1 : RESERVED1
bits : 10 - 41 (32 bit)
access : read-write


TRANS_ADDRESS

cci trans address
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRANS_ADDRESS TRANS_ADDRESS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANSLATION_ADDRESS_VALID TRANSLATION_ADDRESS

TRANSLATION_ADDRESS_VALID : Translation is enabled or not
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Enable

Translation is enabled

1 : Disable

Translation is not enabled

End of enumeration elements list.

TRANSLATION_ADDRESS : Address offset for translation address
bits : 1 - 32 (32 bit)
access : read-write


PREFETCH_CTRL

CCI prefetch control register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_CTRL PREFETCH_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCI_PREFETCH_EN CCI_2X_CLK_ENABLE_FOR_DDR_MODE RESERVED1

CCI_PREFETCH_EN : cci pre-fetch enables on AHB read operation.
bits : 0 - 0 (1 bit)
access : read-write

CCI_2X_CLK_ENABLE_FOR_DDR_MODE : It is an enable for CCI 2x clock in DDR mode
bits : 1 - 2 (2 bit)
access : read-write

RESERVED1 : Reserved1
bits : 2 - 33 (32 bit)
access : read-write


MODE_INTR_STATUS

Interrupt Status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE_INTR_STATUS MODE_INTR_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED1 INTR_CLEAR RESERVED2 INTR_STATUS RESERVED3

RESERVED1 : Reserved1
bits : 0 - 2 (3 bit)
access : read-write

INTR_CLEAR : By setting this bits will clear the interrupt status
bits : 3 - 7 (5 bit)
access : read-write

RESERVED2 : Reserved2
bits : 5 - 15 (11 bit)
access : read-write

INTR_STATUS : These bits will represents the status of the interrupt in read mode
bits : 11 - 23 (13 bit)
access : read-only

RESERVED3 : RESER
bits : 13 - 44 (32 bit)
access : read-write


LSB_A_S1

Lower Address of slave 0 supported
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSB_A_S1 LSB_A_S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWER_ADDRESS

LOWER_ADDRESS : Lower Address of slave 0 supported. Make sure that slave0 is enabled.
bits : 0 - 31 (32 bit)
access : read-write


LSB_A_S2

LOWER Address of slave 0 supported
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSB_A_S2 LSB_A_S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWER_ADDRESS

LOWER_ADDRESS : Lower Address of slave 1 supported. Make sure that slave1 is enabled.
bits : 0 - 31 (32 bit)
access : read-write



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