\n

CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1F byte (0x0)
mem_usage : registers
protection :

Registers

MR

CMR

ACR

AMR

ECC

RXERR

TXERR

ALC

SR

ISR_IACK

IMR

RMC

BTIM0

BTIM1

TXBUF

RXBUF


MR

Mode Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AFM LOM RM RESERVED1

AFM : hardware acceptance filter scheme
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Dual

dual filter is used

1 : Single

single filter is used

End of enumeration elements list.

LOM : Listen Only Mode
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

00 : Disable

Normal mode is set by writing 0 to LOM and 0to RM while in reset mode

01 : Enable

Listen only mode is set by writing 1 to LOM bit and 0 to RM bit while in reset mode

End of enumeration elements list.

RM : Reset Mode
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

00 : Disable

Normal mode or Listen only mode depending on LOM value

01 : Enable

DCAN works in reset mode

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 3 - 10 (8 bit)
access : read-write


CMR

Command Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMR CMR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESERVED1 AT TR RESERVED2

RESERVED1 : Reserved1
bits : 0 - 0 (1 bit)
access : write-only

AT : Abort Transmission
bits : 1 - 2 (2 bit)
access : write-only

TR : Transmit Request
bits : 2 - 4 (3 bit)
access : write-only

Enumeration:

0 : Disable

NONE

01 : Enable

initiates frame transmission by Bit Stream Processor

End of enumeration elements list.

RESERVED2 : Reserved2
bits : 4 - 11 (8 bit)
access : write-only


ACR

ACCEPTANCE CODE REGISTER
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACR0 ACR1 ACR2 ACR3

ACR0 : The acceptance code registers contains bit patterns of messages to be received
bits : 0 - 7 (8 bit)
access : read-write

ACR1 : The acceptance code registers contains bit patterns of messages to be received
bits : 8 - 23 (16 bit)
access : read-write

ACR2 : The acceptance code registers contains bit patterns of messages to be received
bits : 16 - 39 (24 bit)
access : read-write

ACR3 : The acceptance code registers contains bit patterns of messages to be received
bits : 24 - 55 (32 bit)
access : read-write


AMR

ACCEPTANCE MASK REGISTER
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMR AMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMR0 AMR1 AMR2 AMR3

AMR0 : Acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
bits : 0 - 7 (8 bit)
access : read-write

AMR1 : acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
bits : 8 - 23 (16 bit)
access : read-write

AMR2 : acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
bits : 16 - 39 (24 bit)
access : read-write

AMR3 : acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
bits : 24 - 55 (32 bit)
access : read-write


ECC

ERROR CODE CAPTURE REGISTER
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECC ECC read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BER STFER CRCER FRMER ACKER EDIR TXWRN RXWRN

BER : Bit Error occurred
bits : 0 - 0 (1 bit)
access : read-only

STFER : stuff error occurred
bits : 1 - 2 (2 bit)
access : read-only

CRCER : CRC error occurred
bits : 2 - 4 (3 bit)
access : read-only

FRMER : Frame error occurred
bits : 3 - 6 (4 bit)
access : read-only

ACKER : Acknowledgement error occurred
bits : 4 - 8 (5 bit)
access : read-only

EDIR : direction of transfer while error occurred
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : Disable

Transmission

1 : Enable

Reception

End of enumeration elements list.

TXWRN : set when TXERR counter is greater than or equal to 96
bits : 6 - 12 (7 bit)
access : read-only

RXWRN : set when RXERR counter is greater than or equal to 96
bits : 7 - 14 (8 bit)
access : read-only


RXERR

RECEIVE ERROR COUNTER REGISTER
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXERR RXERR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RXERR

RXERR : The RXERR register reflects current value of the receive error counter
bits : 0 - 7 (8 bit)
access : read-only


TXERR

RECEIVE ERROR COUNTER REGISTER
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXERR TXERR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXERR

TXERR : The TXERR register reflects current value of the transmit error counter
bits : 0 - 7 (8 bit)
access : read-only


ALC

ARBITRATION LOST CODE CAPTURE REGISTER
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ALC ALC read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ALC RESERVED1

ALC : Arbitration Lost Capture
bits : 0 - 4 (5 bit)
access : read-only

RESERVED1 : Reserved1
bits : 5 - 12 (8 bit)
access : read-only


SR

Status register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BS ES TS RS RESERVED1 TBS DSO RBS

BS : Bus Off Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : Disable

frame reception and transmission is possible

01 : Enable

node is in bus off state and cannot transmit and receive frames

End of enumeration elements list.

ES : Error Status
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : Disable

NONE

01 : Enable

At least one of CAN error counters reached error warning limit (96).

End of enumeration elements list.

TS : Transmit Status
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

0 : Disable

NONE

01 : Enable

DCAN core is transmitting a message

End of enumeration elements list.

RS : Receive Status
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

0 : Disable

NONE

01 : Enable

DCAN core is receiving a message.

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 4 - 8 (5 bit)
access : read-only

TBS : Transmit Buffer Status
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : Disable

transmit buffer is locked for CPU (ie. message is being transmitted or transmission pending).

01 : Enable

transmit buffer is released for CPU (ie. CPU may write new message into TX buffer).

End of enumeration elements list.

DSO : Data Overrun Status
bits : 6 - 12 (7 bit)
access : read-only

Enumeration:

0 : Disable

no overrun occurred since last clear data overrun command.

1 : Enable

RX FIFO encounters overrun

End of enumeration elements list.

RBS : Data Overrun Status
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

0 : Disable

no messages are in FIFO

01 : Enable

at least one message is in FIFO

End of enumeration elements list.


ISR_IACK

Interrupt Status/Acknowledge Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR_IACK ISR_IACK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DOI BEI TI RI EPI EWI ALI RESERVED1

DOI : Data Overrun Interrupt
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

DOI interrupt write this bit with 1.

1 : Enable

receive FIFO overrun occurred

End of enumeration elements list.

BEI : Bus Error Interrupt
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

BEI interrupt write 1 to this bit.

1 : Enable

DCAN encounters bus error while transmitting or receiving message

End of enumeration elements list.

TI : Transmission Interrupt
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

TI bit must be cleared by CPU by writing 1 to it to reset write pointer to TX RAM before next frame data will be written.

1 : Enable

bit is set high after successful transmission

End of enumeration elements list.

RI : Receive Interrupt
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

CPU must write RI bit with 1 (message read acknowledge), to decrement RX message counter (RMC)

1 : Enable

there is at least one message in the receive FIFO.

End of enumeration elements list.

EPI : Error Passive Interrupt
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Write 1 to EPI clears the Error Passive Interrupt

1 : Enable

CAN bus controller reached or exit error passive level (i.e. on state change active-to-passive or passive-to-active).

End of enumeration elements list.

EWI : Error Warning Interrupt
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disable

Write 1 to EWI to clear interrupt

1 : Enable

CAN bus controller reached or exit error passive level (i.e. on state change active-to-passive or passive-to-active).

End of enumeration elements list.

ALI : Arbitration Lost Interrupt
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

Write 1 to ALI clears this interrupt

1 : Enable

ALI (Arbitration Lost Interrupt) is activated when DCAN core lost arbitration during transmission of its own message and became a receiver.

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 7 - 14 (8 bit)
access : read-write


IMR

Interrupt Mask register.Setting appropriate bit in IMR register enables interrupt assigned to it, clearing disables this interrupt
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DOIM BEIM TIM RIM EPIM EWIM ALIM RESERVED1

DOIM : mask for DOI interrupt
bits : 0 - 0 (1 bit)
access : read-write

BEIM : mask for BEI interrupt
bits : 1 - 2 (2 bit)
access : read-write

TIM : mask for TI interrupt
bits : 2 - 4 (3 bit)
access : read-write

RIM : mask for RI interrupt
bits : 3 - 6 (4 bit)
access : read-write

EPIM : mask for EPI interrupt
bits : 4 - 8 (5 bit)
access : read-write

EWIM : mask for EWI interrupt
bits : 5 - 10 (6 bit)
access : read-write

ALIM : mask for ALI interrupt
bits : 6 - 12 (7 bit)
access : read-write

RESERVED1 : Reserved1
bits : 7 - 14 (8 bit)
access : read-write


RMC

Receive Message Counter
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RMC RMC read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RMC RESERVED1

RMC : number of stored message frames
bits : 0 - 4 (5 bit)
access : read-only

RESERVED1 : Reserved1
bits : 5 - 12 (8 bit)
access : read-only


BTIM0

BUS TIMING REGISTER 0
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTIM0 BTIM0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRP SJW

BRP : Baud Rate Pre scaler
bits : 0 - 5 (6 bit)
access : read-write

SJW : Synchronization Jump Width
bits : 6 - 13 (8 bit)
access : read-write


BTIM1

BUS TIMING REGISTER 1.define the length of bit period, location of the sample point and number of samples to be taken at each sample point
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTIM1 BTIM1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TSEG1 TSEG2 SAM

TSEG1 : Number of clock cycles per Time Segment 1
bits : 0 - 3 (4 bit)
access : read-write

TSEG2 : Number of clock cycles per Time Segment 1
bits : 4 - 10 (7 bit)
access : read-write

SAM : Number of bus level samples
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Disable

bus level is sampled once

1 : Enable

bus level is sampled three times

End of enumeration elements list.


TXBUF

TRANSMIT BUFFER REGISTER
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXBUF TXBUF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBUF0 TXBUF1 TXBUF2 TXBUF3

TXBUF0 : Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
bits : 0 - 7 (8 bit)
access : write-only

TXBUF1 : Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
bits : 8 - 23 (16 bit)
access : write-only

TXBUF2 : Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
bits : 16 - 39 (24 bit)
access : write-only

TXBUF3 : Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
bits : 24 - 55 (32 bit)
access : write-only


RXBUF

RECEIVE BUFFER REGISTER
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXBUF RXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBUF0 RXBUF1 RXBUF2 RXBUF3

RXBUF0 : Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
bits : 0 - 7 (8 bit)
access : read-only

RXBUF1 : Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
bits : 8 - 23 (16 bit)
access : read-only

RXBUF2 : Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
bits : 16 - 39 (24 bit)
access : read-only

RXBUF3 : Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
bits : 24 - 55 (32 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.