Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection :
Quadrature Encoder status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
QEI_INDEX : This is a direct value from the position signal generator
bits : 0 - 0 (1 bit)
access : read-only
QEI_POSITION_B : This is a direct value from the position signal generator.Value refers to the signal Position_B from the generator.
bits : 1 - 2 (2 bit)
access : read-only
QEI_POSITION_A : This is a direct value from the position signal generator.Value refers to the signal Position_A from the generator.
bits : 2 - 4 (3 bit)
access : read-only
POSITION_CNTR_ERR : Count Error Status Flag bit
bits : 3 - 6 (4 bit)
access : read-only
POSITION_CNTR_DIRECTION : Position Counter Direction Status bit
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Disable
Position counter direction is negative (-)
1 : Enable
Position counter direction is positive (+)
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 5 - 36 (32 bit)
access : read-only
Quadrature Encoder index counter register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_INDEX_CNT : Index counter value.User can initialize/change the index counter using this register
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
Quadrature Encoder maximum index counter value register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_INDEX_MAX_CNT : This is a maximum count value that is allowed to increment in the index counter. If index counter reaches this value, will get reset to zero
bits : 0 - 31 (32 bit)
access : read-write
Quadrature Encoder position counter register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_POSITION_CNT_WR_VALUE : This is used to program/change the value of position counter status.In 16-bit mode, only the lower 16 bits are used.
bits : 0 - 31 (32 bit)
access : read-write
Quadrature Encoder maximum position counter value register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_POSITION_MAX_CNT : This is a maximum count value that is allowed to increment in the position counter.
bits : 0 - 31 (32 bit)
access : read-write
Quadrature Encoder interrupt status register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
QEI_POSITION_CNT_RESET_INTR_LEV : This is raised when the position counter reaches it's extremes
bits : 0 - 0 (1 bit)
access : read-only
QEI_INDEX_CNT_MATCH_INTR_LEV : This is raised when index counter reaches max value loaded in to index_max_cnt register.
bits : 1 - 2 (2 bit)
access : read-only
POSITION_CNTR_ERR_INTR_LEV : Whenever number of possible positions are mismatched with actual positions are received between two index pulses this will raised
bits : 2 - 4 (3 bit)
access : read-only
VELOCITY_LESS_THAN_INTR_LEV : When velocity count is less than the value given in velocity_value_to_compare register, interrupt is raised
bits : 3 - 6 (4 bit)
access : read-only
QEI_POSITION_CNT_MATCH_INTR_LEV : This is raised when the position counter reaches position match value, which is programmable.
bits : 4 - 8 (5 bit)
access : read-only
QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV : When velocity count is computed for given delta time, than interrupt is raised.
bits : 5 - 10 (6 bit)
access : read-only
RESERVED1 : Reserved1
bits : 6 - 37 (32 bit)
access : read-only
Quadrature Encoder interrupt acknowledge register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_POSITION_CNT_RESET_INTR_LEV : Qei_position_cnt_reset_intr_ack
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
No effect.
1 : Enable
Qei position cnt reset intr will be cleared.
End of enumeration elements list.
QEI_INDEX_CNT_MATCH_INTR_LEV : NONE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
No effect.
1 : Enable
Qei index cnt match intr will be cleared.
End of enumeration elements list.
POSITION_CNTR_ERR_INTR_LEV : Position_cntr_err_intr_ack
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
No effect.
1 : Enable
Position cntr err intr will be cleared.
End of enumeration elements list.
VELOCITY_LESS_THAN_INTR_LEV : Velocity_less_than_intr_ack
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
No effect.
1 : Enable
Velocity less than intr will be cleared
End of enumeration elements list.
QEI_POSITION_CNT_MATCH_INTR_LEV : Qei_position_cnt_match_intr_ack
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
No effect.
1 : Enable
Qei position cnt match intr will be cleared.
End of enumeration elements list.
VELOCITY_COMPUTATION_OVER_INTR_LEV : Velocity_computation_over_intr_ack
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
No effect.
1 : Enable
Velocity computation is over intr will be cleared.
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 6 - 37 (32 bit)
access : read-write
Quadrature Encoder interrupt mask register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_POSITION_CNT_RESET_INTR_MASK : Qei_position_cnt_reset_intr_mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
If read : Qei position cnt reset intr is not given on qei_intr pin. If write: No effect
1 : Enable
If read : Qei position cnt reset intr is given on qei_intr pin If write: Qei position cnt reset intr will not be given on qei_intr pin
End of enumeration elements list.
QEI_INDEX_CNT_MATCH_INTR_MASK : Qei_index_cnt_match_intr_mask
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
If read : Qei index cnt match intr is not given on qei_intr pin If write: No effect
1 : Enable
If read : Qei index cnt match intr is given on qei_intr pin. If write: Qei index cnt match intr will not be given on qei_intr pin.
End of enumeration elements list.
POSITION_CNTR_ERR_INTR_MASK : Position_cntr_err_intr_mask
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
If read : Position cntr err intr is not given on qei_intr pin. If write: No effect
1 : Enable
If read : Position cntr err intr is given on qei_intr pin. If write: Position cntr err intr will not be given on qei_intr pin
End of enumeration elements list.
VELOCITY_LESS_THAN_INTR_MASK : Velocity_less_than_intr_mask
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
If read : Velocity less than intr is not given on qei_intr pin. If write: No effect
1 : Enable
If read :Velocity less than intr is given on qei_intr pin. If write: Velocity less than intr will not be given on qei_intr pin.
End of enumeration elements list.
QEI_POSITION_CNT_MATCH_INTR_MASK : Qei_position_cnt_match_intr_mask
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
If read :Qei position cnt match intr is given on qei_intr pin If write: No effect
1 : Enable
If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin
End of enumeration elements list.
VELOCITY_COMPUTATION_OVER_INTR_MASK : Velocity_computation_over_intr_mask
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
If read :Qei position cnt match intr is given on qei_intr pin If write: No effect
1 : Enable
If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 6 - 37 (32 bit)
access : read-write
Quadrature Encoder interrupt unmask register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_POSITION_CNT_RESET_INTR_UNMASK : Qei_position_cnt_reset_intr_unmask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
If read : Qei position cnt reset intr is not given on qei_intr pin. If write: No effect
1 : Enable
If read : Qei position cnt reset intr is given on qei_intr pin If write: Qei position cnt reset intr will not be given on qei_intr pin
End of enumeration elements list.
QEI_INDEX_CNT_MATCH_INTR_UNMASK : Qei_index_cnt_match_intr_unmask
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
If read : Qei index cnt match intr is not given on qei_intr pin If write: No effect
1 : Enable
If read : Qei index cnt match intr is given on qei_intr pin. If write: Qei index cnt match intr will not be given on qei_intr pin.
End of enumeration elements list.
POSITION_CNTR_ERR_INTR_UNMASK : Position_cntr_err_intr_unmask
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
If read : Position cntr err intr is not given on qei_intr pin. If write: No effect
1 : Enable
If read : Position cntr err intr is given on qei_intr pin. If write: Position cntr err intr will not be given on qei_intr pin
End of enumeration elements list.
VELOCITY_LESS_THAN_INTR_UNMASK : Velocity_less_than_intr_unmask
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
If read : Velocity less than intr is not given on qei_intr pin. If write: No effect
1 : Enable
If read :Velocity less than intr is given on qei_intr pin. If write: Velocity less than intr will not be given on qei_intr pin.
End of enumeration elements list.
QEI_POSITION_CNT_MATCH_INTR_UNMASK : Qei_position_cnt_match_intr_unmask
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
If read :Qei position cnt match intr is given on qei_intr pin If write: No effect
1 : Enable
If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 5 - 36 (32 bit)
access : read-write
Quadrature Encoder clock frequency register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_CLK_FREQ : Indication of clock frequency on which QEI controller is running.
bits : 0 - 8 (9 bit)
access : read-write
RESERVED1 : Reserved1
bits : 9 - 40 (32 bit)
access : read-write
Quadrature Delta time register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELTA_TIME_FOR_VELOCITY : Delta time LSW to compute velocity
bits : 0 - 19 (20 bit)
access : read-write
RESERVED1 : Reserved1
bits : 20 - 51 (32 bit)
access : read-write
Quadrature Encoder control set register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_SFT_RST : Quadrature encoder soft reset. It is self reset signal.
bits : 0 - 0 (1 bit)
access : read-only
QEI_SWAP_PHASE_AB : Phase A and Phase B Input Swap Select bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Phase A and Phase B inputs are not swapped
1 : Enable
Phase A and Phase B inputs are swapped
End of enumeration elements list.
POS_CNT_RST_WITH_INDEX_EN : Phase A and Phase B Input Swap Select bit
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
position counter is getting reset after reaching max count, which is mentioned in position_max_cnt
1 : Enable
position counter is getting reset for every index pulse
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 3 - 6 (4 bit)
access : read-write
POS_CNT_DIRECTION_CTRL : NONE
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
position B pin defines the direction of position counter
1 : Enable
pos_cnt_dir_frm_reg defines the position counter direction
End of enumeration elements list.
POS_CNT_DIR_FRM_REG : Position Counter Direction indication from user
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Position counter direction is negative (-)
1 : Enable
Position counter direction is positive (+)
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 6 - 12 (7 bit)
access : read-write
RESERVED3 : Reserved3
bits : 7 - 14 (8 bit)
access : read-write
INDEX_CNT_RST_EN : Index count reset enable
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
NONE
1 : Enable
index counter is going to reset after reaching max count, which is mentioned in qei_index_max_cnt register.
End of enumeration elements list.
DIGITAL_FILTER_BYPASS : NONE
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
digital filter is in-path for all input signals
1 : Enable
digital filter is bypassed for all input signals (position A, position B and Index)
End of enumeration elements list.
TIMER_MODE : NONE
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Quadrature encoder mode
1 : Enable
timer mode. In this mode, decoded timer pulse and direction are taken from position A and position B pins respectively.
End of enumeration elements list.
START_VELOCITY_CNTR : Starting the velocity counter. It is self reset bit.
bits : 11 - 22 (12 bit)
access : read-write
QEI_STOP_IN_IDLE : NONE
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
QEI position status counter is working as 32 bit counter.
1 : Enable
QEI position status counter is working as 16 bit counter
End of enumeration elements list.
QEI_POS_CNT_16_BIT_MODE : Qei position counter 16 bit mode enable
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
No effect
1 : Enable
QEI position status counter will be working as a 16 bit counter
End of enumeration elements list.
POS_CNT_RST : 1=position counter is going to reset
bits : 14 - 28 (15 bit)
access : read-write
INDEX_CNT_RST : 1= index counter is going to reset.
bits : 15 - 30 (16 bit)
access : read-write
RESERVED4 : Reserved4
bits : 16 - 47 (32 bit)
access : read-write
Quadrature velocity register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VELOCITY_VALUE_TO_COMPARE : For read operation :It is the velocity count to compare using TA firmware For write operation :It is the velocity value to compare with velocity count
bits : 0 - 31 (32 bit)
access : read-write
Quadrature position match register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSTION_MATCH_VALUE : Position match value to compare the position counter.
bits : 0 - 31 (32 bit)
access : read-write
Quadrature Encoder control reset register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_SFT_RST : Quadrature encoder soft reset. It is self reset signal
bits : 0 - 0 (1 bit)
access : read-only
QEI_SWAP_PHASE_AB : Phase A and Phase B Input Swap Select bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Phase A and Phase B inputs are not swapped
1 : Enable
Phase A and Phase B inputs are swapped
End of enumeration elements list.
POS_CNT_RST_WITH_INDEX_EN : Phase A and Phase B Input Swap Select bit
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
position counter is getting reset after reaching max count, which is mentioned in position_max_cnt
1 : Enable
position counter is getting reset for every index pulse
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 3 - 6 (4 bit)
access : read-write
POS_CNT_DIRECTION_CTRL : NONE
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
position B pin defines the direction of position counter
1 : Enable
pos_cnt_dir_frm_reg defines the position counter direction
End of enumeration elements list.
POS_CNT_DIR_FRM_REG : Position Counter Direction indication from user
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Position counter direction is negative (-)
1 : Enable
Position counter direction is positive (+)
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 6 - 12 (7 bit)
access : read-write
RESERVED3 : Reserved3
bits : 7 - 14 (8 bit)
access : read-write
INDEX_CNT_RST_EN : NONE
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
NONE
1 : Enable
index counter is going to reset after reaching max count, which is mentioned in qei_index_max_cnt register.
End of enumeration elements list.
DIGITAL_FILTER_BYPASS : NONE
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
digital filter is in-path for all input signals
1 : Enable
digital filter is bypassed for all input signals (position A, position B and Index)
End of enumeration elements list.
TIMER_MODE : NONE
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Quadrature encoder mode
1 : Enable
timer mode. In this mode, decoded timer pulse and direction are taken from position A and position B pins respectively
End of enumeration elements list.
START_VELOCITY_CNTR : Starting the velocity counter. It is self reset bit.
bits : 11 - 22 (12 bit)
access : read-write
QEI_STOP_IN_IDLE : NONE
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
QEI position status counter is working as 32 bit counter.
1 : Enable
QEI position status counter is working as 16 bit counter
End of enumeration elements list.
QEI_POS_CNT_16_BIT_MODE : Qei position counter 16 bit mode enable
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
No effect
1 : Enable
QEI position status counter will be working as a 16 bit counter
End of enumeration elements list.
POS_CNT_RST : 1=position counter is going to reset
bits : 14 - 28 (15 bit)
access : read-write
INDEX_CNT_RST : 1= index counter is going to reset.
bits : 15 - 30 (16 bit)
access : read-write
RESERVED4 : Reserved4
bits : 16 - 47 (32 bit)
access : read-write
Quadrature Encoder initialization register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_ENCODING_MODE : NONE
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 00
1x mode
1 : 01
2x mode
2 : 10
4x mode
3 : 11
NONE
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 2 - 5 (4 bit)
access : read-write
INDEX_MATCH_VALUE : These bits allow user to specify the state of position A and B during index pulse generation.
bits : 4 - 9 (6 bit)
access : read-write
DF_CLK_DIVIDE_SLT : Digital Filter Clock Divide Select bits
bits : 6 - 15 (10 bit)
access : read-write
Enumeration:
0 : 0000
0000 = 1:1 Clock divide for Index, position A and B
1 : 0001
0001 = 1:2 Clock divide for Index, position A and B
2 : 0010
0010 = 1:4 Clock divide for Index, position A and B
3 : 0011
0011 = 1:8 Clock divide for Index, position A and B
4 : 0100
0100 = 1:16 Clock divide for Index, position A and B
5 : 0101
0101 = 1:32 Clock divide for Index, position A and B
6 : 0110
0110 = 1:64 Clock divide for Index, position A and B
7 : 0111
0111 = 1:128 Clock divide for Index, position A and B
8 : 1000
1000 = 1:256 Clock divide for Index, position A and B
9 : 1001
1001 = 1:512 Clock divide for Index, position A and B
10 : 1010
1010 = 1:1024 Clock divide for Index, position A and B
End of enumeration elements list.
UNIDIRECTIONAL_VELOCITY : Uni directional velocity enable.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
NONE
1 : Enable
1 means direction change in position counter resets velocity counter
End of enumeration elements list.
UNIDIRECTIONAL_INDEX : Uni directional index enable.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
NONE
1 : Enable
1 means direction change in position counter resets index counter
End of enumeration elements list.
INDEX_CNT_INIT : Index counter initial value in unidirectional index enable mode.
bits : 12 - 24 (13 bit)
access : read-write
RESERVED2 : Reserved2
bits : 13 - 44 (32 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.