\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :
Divisor Latch Low
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLL : Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART.
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Transmit Holding Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : DLL
reset_Mask : 0x0
THR : Data to be transmitted on serial output port
bits : 0 - 7 (8 bit)
access : write-only
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : write-only
Receive Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : DLL
reset_Mask : 0x0
RBR : Receive Buffer Field
bits : 0 - 7 (8 bit)
access : read-only
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Modem Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTR : This is used to directly control the Data Terminal Ready (dtr_n) output
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DTR_LOGIC1
dtr_n de-asserted (logic 1)
1 : DTR_LOGIC0
dtr_n asserted (logic 0)
End of enumeration elements list.
RTS : This is used to directly control the Request to Send (rts_n) output
bits : 1 - 2 (2 bit)
access : read-write
OUT1 : This is used to directly control the user-designated Output1 (out1_n) output
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : OUT1_LOGIC1
out1_n de-asserted (logic 1)
1 : OUT1_LOGIC0
out1_n asserted (logic 0)
End of enumeration elements list.
OUT2 : This is used to directly control the user-designated Output2 (out2_n) output
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : OUT2_LOGIC1
out2_n de-asserted (logic 1)
1 : OUT2_LOGIC0
out2_n asserted (logic 0)
End of enumeration elements list.
LB : This is used to put the UART into a diagnostic mode for test purposes
bits : 4 - 8 (5 bit)
access : read-write
AFCE : This is used to directly control the user-designated Output2 (out2_n) output
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disabled
Auto Flow Control Mode disabled
1 : Enabled
Auto Flow Control Mode enabled
End of enumeration elements list.
SIRE : This is used to enable/disable the IrDA SIR Mode features
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disabled
IrDA SIR Mode disabled
1 : Enabled
IrDA SIR Mode enabled
End of enumeration elements list.
RESERVED1 : reserved1
bits : 7 - 38 (32 bit)
access : read-only
Line Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DR : This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Disabled
No data Ready
1 : Enabled
Data Ready
End of enumeration elements list.
OE : This is used to indicate the occurrence of an overrun error
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : Disabled
no overrun error
1 : Enabled
overrun error
End of enumeration elements list.
PE : This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : Disabled
no parity error
1 : Enabled
parity error
End of enumeration elements list.
FE : This is used to indicate the occurrence of a framing error in the receiver
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : Disabled
no framing error
1 : Enabled
framing error
End of enumeration elements list.
BI : his is used to indicate the detection of a break sequence on the serial input data
bits : 4 - 8 (5 bit)
access : read-only
THRE : Transmit Holding Register Empty bit
bits : 5 - 10 (6 bit)
access : read-only
TEMT : Transmitter Empty bit
bits : 6 - 12 (7 bit)
access : read-only
RFE : This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0 : Disabled
no error in RX FIFO
1 : Enabled
error in RX FIFO
End of enumeration elements list.
ADDRRCVD : Address Received bit
bits : 8 - 16 (9 bit)
access : read-only
RESERVED1 : reserved1
bits : 9 - 40 (32 bit)
access : read-only
Modem Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCTS : This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Disabled
no change on cts_n since last read of MSR
1 : Enabled
change on cts_n since last read of MSR
End of enumeration elements list.
DDSR : This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : Disabled
no change on dsr_n since last read of MSR
1 : Enabled
change on dsr_n since last read of MSR
End of enumeration elements list.
TERI : This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state) has occurred since the last time the MSR was read
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : Disabled
no change on ri_n since last read of MSR
1 : Enabled
change on ri_n since last read of MSR
End of enumeration elements list.
DDCD : This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : Disabled
no change on dcd_n since last read of MSR
1 : Enabled
change on dcd_n since last read of MSR
End of enumeration elements list.
CTS : This is used to indicate the current state of the modem control line cts_n
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Disabled
cts_n input is de-asserted (logic 1)
1 : Enabled
cts_n input is asserted (logic 0)
End of enumeration elements list.
DSR : This is used to indicate the current state of the modem control line dsr_n
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : Disabled
dsr_n input is de-asserted (logic 1)
1 : Enabled
dsr_n input is asserted (logic 0)
End of enumeration elements list.
RI : This is used to indicate the current state of the modem control line ri_n
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : Disabled
ri_n input is de-asserted (logic 1)
1 : Enabled
ri_n input is asserted (logic 0)
End of enumeration elements list.
DCD : This is used to indicate the current state of the modem control line dcd_n
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0 : Disabled
dcd_n input is de-asserted (logic 1)
1 : Enabled
dcd_n input is asserted (logic 0)
End of enumeration elements list.
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Scratch pad Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH_PAD : This register is for programmers to use as a temporary storage space. It has no defined purpose
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Low Power Divisor Latch Low Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW_POWER_DLL : This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Low Power Divisor Latch High Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW_POWER_DLH : This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERBFI : Enable Received Data Available Interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Received Data Available Interrupt is disabled
1 : Enable
Received Data Available Interrupt is enabled
End of enumeration elements list.
ETBEI : Enable Transmit Holding Register Empty Interrupt
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Transmit Holding Register Empty Interrupt is disabled
1 : Enable
Transmit Holding Register Empty Interrupt is enabled
End of enumeration elements list.
ELSI : Enable Receiver Line Status Interrupt
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Receiver Line Status Interrupt is disabled
1 : Enable
Receiver Line Status Interrupt is enabled
End of enumeration elements list.
EDSSI : Enable Modem Status Interrupt
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Modem Status Interrupt is disabled
1 : Enable
Modem Status Interrupt is enabled
End of enumeration elements list.
RESERVED1 : reserved1
bits : 4 - 10 (7 bit)
access : read-only
PTIME : Programmable THRE Interrupt Mode Enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
generation of THRE Interrupt is disabled
1 : Enable
generation of THRE Interrupt is enabled
End of enumeration elements list.
RESERVED2 : reserved2
bits : 8 - 39 (32 bit)
access : read-only
Divisor Latch High
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : IER
reset_Mask : 0x0
DLH : Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
none
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_DUPLEX_MODE : none
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : ENABLE
Full duplex mode enable
0 : DISABLE
Full duplex mode disable
End of enumeration elements list.
TX_MODE_RX_MODE : This signal is valid when full_duplex_mode is disabled
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : tx_mode
tx_mode
1 : rx_mode
rx_mode
End of enumeration elements list.
RESERVED1 : reserved1
bits : 2 - 33 (32 bit)
access : read-only
none
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC_MODE : none
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SYNC_MODE
Sync mode
0 : NON_SYNC_MODE
Non-Sync mode
End of enumeration elements list.
MST_MODE : none
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : MST_MODE
MST mode
0 : NON_MST_MODE
Non-MST mode
End of enumeration elements list.
CONTI_CLK_MODE : none
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : CONTINUOUS_CLK_MODE
Continuous clock mode
0 : NON_CONTINUOUS_CLK_MODE
Non-continuous clock mode
End of enumeration elements list.
START_STOP_EN : none
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : ENABLE_START_STOP
Enable start stop
0 : DISABLE_START_STOP
Disable start stop
End of enumeration elements list.
RESERVED1 : reserved1
bits : 6 - 37 (32 bit)
access : read-only
none
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC_MODE : none
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FIFO_ACCESS_DISABLE
FIFO access mode disabled
1 : FIFO_ACCESS_ENABLE
FIFO access mode enabled
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
none
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TX_FIFO_RD : Transmit FIFO Read
bits : 0 - 7 (8 bit)
access : read-only
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
none
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RFWD : Receive FIFO Write Data
bits : 0 - 7 (8 bit)
access : read-write
RFPE : Receive FIFO Parity Error
bits : 8 - 16 (9 bit)
access : read-write
RFFE : Receive FIFO Framing Error
bits : 9 - 18 (10 bit)
access : read-write
RESERVED1 : reserved1
bits : 10 - 41 (32 bit)
access : read-only
UART Status Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
BUSY : Indicates that a serial transfer is in progress
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Disabled
UART is idle or inactive
1 : Enabled
UART is busy (actively transferring data)
End of enumeration elements list.
TFNF : To Indicate that the transmit FIFO is not full
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : Disabled
Transmit FIFO is full
1 : Enabled
Transmit FIFO is not full
End of enumeration elements list.
TFE : To Indicate that the transmit FIFO is completely empty
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : Disabled
Transmit FIFO is not empty
1 : Enabled
Transmit FIFO is empty
End of enumeration elements list.
RFNE : To Indicate that the receive FIFO contains one or more entries
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : Disabled
Receive FIFO is empty
1 : Enabled
Receive FIFO is not empty
End of enumeration elements list.
RFE : To Indicate that the receive FIFO is completely full
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Disabled
Receive FIFO not full
1 : Enabled
Receive FIFO Full
End of enumeration elements list.
RESERVED1 : reserved1
bits : 5 - 36 (32 bit)
access : read-only
FIFO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIFOE : This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs
bits : 0 - 0 (1 bit)
access : write-only
RFIFOR : RCVR FIFO Reset
bits : 1 - 2 (2 bit)
access : write-only
XFIFOR : XMIT FIFO Reset
bits : 2 - 4 (3 bit)
access : write-only
DMAM : DMA signalling mode
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : Mode0
DMA Signalling mode0
1 : Mode1
DMA Signalling mode1
End of enumeration elements list.
TET : TX Empty Trigger
bits : 4 - 9 (6 bit)
access : write-only
Enumeration:
0 : FIFO_EMPTY
FIFO Empty
1 : FIFO_2_CHARACTER
2 characters in the FIFO
2 : FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
3 : FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
End of enumeration elements list.
RT : This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated
bits : 6 - 13 (8 bit)
access : write-only
Enumeration:
0 : FIFO_1_CHARACTER
1 character in the FIFO
1 : FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
2 : FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
3 : FIFO_LESS_THAN_2_CHARACTER
FIFO 2 less than full
End of enumeration elements list.
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : write-only
Interrupt Identity Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
IID : Interrupt ID
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : 0000
modem status pending pending interrupt
1 : 0001
This field indicates no interrupt pending status
2 : 0010
Transmit Holding Register Empty pending interrupt
4 : 0100
Received Data Available pending interrupt
6 : 0110
Receive line status pending interrupt
7 : 0111
Busy detect pending interrupt
12 : 1100
Character Timeout pending interrupt
End of enumeration elements list.
RESERVED1 : reserved1
bits : 4 - 9 (6 bit)
access : read-only
FIFOSE : This is used to indicate whether the FIFOs are enabled or disabled.
bits : 6 - 13 (8 bit)
access : read-only
Enumeration:
0 : Disable
FIFO is disabled
1 : Enable
FIFO is enabled
End of enumeration elements list.
RESERVED2 : reserved2
bits : 8 - 39 (32 bit)
access : read-only
Transmit FIFO Level
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
FIFO_ADDR_WIDTH : Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.
bits : 0 - 29 (30 bit)
access : read-only
RESERVED1 : reserved1
bits : 30 - 61 (32 bit)
access : read-only
Receive FIFO Level
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
FIFO_ADDR_WIDTH : Receive FIFO Level. This is indicates the number of data entries in the receive FIFO.
bits : 0 - 29 (30 bit)
access : read-only
RESERVED1 : reserved1
bits : 30 - 61 (32 bit)
access : read-only
Software Reset Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
UR : UART Reset
bits : 0 - 0 (1 bit)
access : write-only
RFR : RCVR FIFO Reset
bits : 1 - 2 (2 bit)
access : write-only
XFR : XMIT FIFO Reset
bits : 2 - 4 (3 bit)
access : write-only
RESERVED1 : reserved1
bits : 3 - 34 (32 bit)
access : write-only
Shadow Request to Send
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTS : Shadow Request to Send.
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Shadow Break Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBCR : Shadow Break Control Bit
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Shadow DMA Mode
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMAM : Shadow DMA Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MODE0
mode 0
1 : MODE1
mode 1
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Shadow FIFO Enable
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFE : Shadow FIFO Enable
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Shadow RCVR Trigger
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRT : Shadow RCVR Trigger
bits : 0 - 1 (2 bit)
access : read-write
RESERVED1 : reserved1
bits : 2 - 33 (32 bit)
access : read-only
Shadow TX Empty Trigger
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STET : Shadow TX Empty Trigger
bits : 0 - 1 (2 bit)
access : read-write
RESERVED1 : reserved1
bits : 2 - 33 (32 bit)
access : read-only
Halt Transmit
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALT_TX : This register is use to halt transmissions for testing
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Halt TX disabled
1 : Enabled
Halt TX enabled
End of enumeration elements list.
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
DMA Software Acknowledge
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SOFTWARE_ACK : This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition
bits : 0 - 0 (1 bit)
access : write-only
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Transceiver Control Register.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RS485_EN : RS485 Transfer Enable.
bits : 0 - 0 (1 bit)
access : read-write
RE_POL : Receiver Enable Polarity.
bits : 1 - 2 (2 bit)
access : read-write
DE_POL : Driver Enable Polarity.
bits : 2 - 4 (3 bit)
access : read-write
XFER_MODE : Transfer Mode.
bits : 3 - 7 (5 bit)
access : read-write
RESERVED1 : reserved1
bits : 5 - 36 (32 bit)
access : read-only
Driver Output Enable Register.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DE_EN : DE Enable control.
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Receiver Output Enable Register.
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RE_EN : RE Enable control.
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : reserved1
bits : 1 - 32 (32 bit)
access : read-only
Driver Output Enable Timing Register.
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DE_ASSERT_TIME : Driver enable assertion time.
bits : 0 - 7 (8 bit)
access : read-write
RES : reserved.
bits : 8 - 23 (16 bit)
DE_DE_ASSERT_TIME : Driver enable de-assertion time.
bits : 16 - 39 (24 bit)
access : read-write
RESERVED1 : reserved1
bits : 24 - 55 (32 bit)
access : read-only
TurnAround Timing Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DE_RE : Driver Enable to Receiver Enable TurnAround time.
bits : 0 - 15 (16 bit)
access : read-write
RE_DE : Receiver Enable to Driver Enable TurnAround time.
bits : 16 - 47 (32 bit)
access : read-write
Line Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLS : Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 5_BITS_PER_CHARACTER
5 bits per character
1 : 6_BITS_PER_CHARACTER
6 bits per character
2 : 7_BITS_PER_CHARACTER
7 bits per character
3 : 8_BITS_PER_CHARACTER
8 bits per character
End of enumeration elements list.
STOP : This is used to select the number of stop bits per character that the peripheral transmits and receives
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 1_STOP_BIT_PER_CHARACTER
1 stop bit per character
1 : 1.5_OR_2_STOPS_BIT_PER_CHARACTER
1.5 or 2 stop bits per character
End of enumeration elements list.
PEN : This bit is used to enable and disable parity generation and detection in transmitted and received serial character
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Parity disabled
1 : Enable
Parity Enabled
End of enumeration elements list.
EPS : This is used to select between even and odd parity
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Set to 0
An odd number of logic 1s is transmitted or checked
1 : Set to 1
An even number of logic 1s is transmitted or checked
End of enumeration elements list.
STICK_PARITY : This bit is used to force parity value
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : LOGIC0
When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0
1 : LOGIC1
If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1
End of enumeration elements list.
BC : This is used to cause a break condition to be transmitted to the receiving device
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : SERIAL_OUTPUT_SPACING_STATE
If set to 1, the serial output is forced to the spacing (logic 0) state
End of enumeration elements list.
DLAB : This bit is used to enable reading and writing of the Divisor Latch register to set the baud rate of the UART
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : INIT_BAUD_RATE_SET
This bit must be cleared after initial baud rate set up
End of enumeration elements list.
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Divisor Latch Fraction Register.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DLF : Fractional part of divisor.
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only
Receive Address Register.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RAR : This is an address matching register during receive mode.
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Transmit Address Register.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RAR : This is an address matching register during receive mode.
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
Line Extended Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DLS_E : Extension for DLS.
bits : 0 - 0 (1 bit)
access : read-write
ADDR_MATCH : Address Match Mode.
bits : 1 - 2 (2 bit)
access : read-write
SEND_ADDR : Send address control bit.
bits : 2 - 4 (3 bit)
access : read-write
TRANSMIT_MODE : Transmit mode control bit.
bits : 3 - 6 (4 bit)
access : read-write
RESERVED1 : reserved1
bits : 4 - 35 (32 bit)
access : read-only
Component Parameter Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
APB_DATA_WIDTH : APB data width register.
bits : 0 - 1 (2 bit)
access : read-only
RESERVED1 : reserved1
bits : 2 - 5 (4 bit)
access : read-only
AFCE_MODE : none
bits : 4 - 8 (5 bit)
access : read-only
THRE_MODE : none
bits : 5 - 10 (6 bit)
access : read-only
SIR_MODE : none
bits : 6 - 12 (7 bit)
access : read-only
SIR_LP_MODE : none
bits : 7 - 14 (8 bit)
access : read-only
ADDITIONAL_FEAT : none
bits : 8 - 16 (9 bit)
access : read-only
FIFO_ACCESS : none
bits : 9 - 18 (10 bit)
access : read-only
FIFO_STAT : none
bits : 10 - 20 (11 bit)
access : read-only
SHADOW : none
bits : 11 - 22 (12 bit)
access : read-only
UART_ADD_ENCODED_PARAMS : none
bits : 12 - 24 (13 bit)
access : read-only
DMA_EXTRA : none
bits : 13 - 26 (14 bit)
access : read-only
RESERVED2 : reserved2
bits : 14 - 29 (16 bit)
access : read-only
FIFO_MODE : none
bits : 16 - 39 (24 bit)
access : read-only
RESERVED3 : reserved3
bits : 24 - 55 (32 bit)
access : read-only
UART Component Version
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
UART_COMP_VER : ASCII value for each number in the version, followed by *
bits : 0 - 31 (32 bit)
access : read-only
Component Type Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
UART_COMP_VER : This register contains the peripherals identification code.
bits : 0 - 31 (32 bit)
access : read-only
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