Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC0 byte (0x0)
mem_usage : registers
protection :
GSPI Clock Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_CLK_SYNC : If the clock frequency to FLASH (spi_clk) and SOC clk is same.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Divided SOC clock is connected SCLK. Division value is programmable
1 : Enable
SCLK clock and SOC clock are same
1 : Enable
SCLK clock and SOC clock are same
1 : Enable
SCLK clock and SOC clock are same
1 : Enable
SCLK clock and SOC clock are same
End of enumeration elements list.
GSPI_CLK_EN : GSPI clock enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Dynamic clock gating is enabled in side GSPI controller
1 : Enable
Full time clock is enabled for GSPI controller.
End of enumeration elements list.
RESERVED1 : reserved for future use
bits : 2 - 33 (32 bit)
access : read-write
GSPI Configuration 1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_MANUAL_CSN : SPI CS in manual mode
bits : 0 - 0 (1 bit)
access : read-write
GSPI_MANUAL_WR : Write enable for manual mode when CS is low.
bits : 1 - 2 (2 bit)
access : read-write
GSPI_MANUAL_RD : Read enable for manual mode when CS is low
bits : 2 - 4 (3 bit)
access : read-write
GSPI_MANUAL_RD_CNT : Indicates total number of bytes to be read
bits : 3 - 15 (13 bit)
access : read-write
GSPI_MANUAL_CSN_SELECT : Indicates which CSn is valid. Can be programmable in manual mode
bits : 13 - 27 (15 bit)
access : read-write
SPI_FULL_DUPLEX_EN : Full duplex mode enable
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : Disable
Full duplex mode disabled.
1 : Enable
Full duplex mode enabled
End of enumeration elements list.
RESERVED1 : reserved for future use
bits : 16 - 47 (32 bit)
access : read-write
GSPI Manual Configuration 2 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_WR_DATA_SWAP_MNL_CSN0 : Swap the write data inside the GSPI controller it-self.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Manual write data swap is disabled for csn0.
1 : Enable
Manual write data swap is enabled for csn0.
End of enumeration elements list.
GSPI_WR_DATA_SWAP_MNL_CSN1 : Swap the write data inside the GSPI controller it-self.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Manual write data swap is disabled for csn1
1 : Enable
Manual write data swap is enabled for csn1
End of enumeration elements list.
GSPI_WR_DATA_SWAP_MNL_CSN2 : Swap the write data inside the GSPI controller it-self.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Manual write data swap is disabled for csn2
1 : Enable
Manual write data swap is enabled for csn2
End of enumeration elements list.
GSPI_WR_DATA_SWAP_MNL_CSN3 : Swap the write data inside the GSPI controller it-self.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Manual write data swap is disabled for csn3
1 : Enable
Manual write data swap is enabled for csn3
End of enumeration elements list.
GSPI_RD_DATA_SWAP_MNL_CSN0 : Swap the read data inside the GSPI controller it-self.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Manual read data swap is disabled for csn0
1 : Enable
Manual read data swap is enabled for csn0
End of enumeration elements list.
GSPI_RD_DATA_SWAP_MNL_CSN1 : Swap the read data inside the GSPI controller it-self.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Manual read data swap is disabled for csn1
1 : Enable
Manual read data swap is enabled for csn1
End of enumeration elements list.
GSPI_RD_DATA_SWAP_MNL_CSN2 : Swap the read data inside the GSPI controller it-self.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Manual read data swap is disabled for csn2
1 : Enable
Manual read data swap is enabled for csn2
End of enumeration elements list.
GSPI_RD_DATA_SWAP_MNL_CSN3 : Swap the read data inside the GSPI controller it-self.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Manual read data swap is disabled for csn3
1 : Enable
Manual read data swap is enabled for csn3
End of enumeration elements list.
GSPI_MANUAL_SIZE_FRM_REG : Manual reads and manual writes
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
1 Byte 8 bit mode
1 : Enable
2 Bytes 16 bit mode
End of enumeration elements list.
RESERVED1 : reserved for future use
bits : 9 - 18 (10 bit)
access : read-write
TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG : NONE
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
No action
1 : Enable
Take write size from Manual config register1[20:19]
End of enumeration elements list.
MANUAL_GSPI_MODE : Internally the priority is given to manual mode
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
SPI mode
1 : Enable
Host SPI mode
End of enumeration elements list.
RESERVED2 : reserved for future use
bits : 12 - 43 (32 bit)
access : read-write
GSPI Write Data 2 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_MANUAL_WRITE_DATA2 : Number of bits to be written in write mode
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : reserved for future use
bits : 4 - 10 (7 bit)
access : read-write
USE_PREV_LENGTH : Use previous length
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
No action
1 : Enable
Uses previously programmed length in [3:0] of this register for next writes
End of enumeration elements list.
RESERVED2 : reserved for future use
bits : 8 - 39 (32 bit)
access : read-write
GSPI FIFO Threshold Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_AEMPTY_THRLD : FIFO almost empty threshold
bits : 0 - 3 (4 bit)
access : read-write
FIFO_AFULL_THRLD : FIFO almost full threshold
bits : 4 - 11 (8 bit)
access : read-write
WFIFO_RESET : Write FIFO reset
bits : 8 - 16 (9 bit)
access : read-write
RFIFO_RESET : read FIFO reset
bits : 9 - 18 (10 bit)
access : read-write
RESERVED1 : reserved for future use
bits : 10 - 41 (32 bit)
access : read-write
GSPI Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GSPI_BUSY : State of Manual mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Disable
GSPI controller is IDLE in Manual mode.
1 : Enable
A read, write or dummy cycle operation is in process in manual mode
End of enumeration elements list.
FIFO_FULL_WFIFO_S : Full status indication for Wfifo in manual mode
bits : 1 - 2 (2 bit)
access : read-only
FIFO_AFULL_WFIFO_S : Almost full status indication for Wfifo in manual mode
bits : 2 - 4 (3 bit)
access : read-only
FIFO_EMPTY_WFIFO : Empty status indication for Wfifo in manual mode
bits : 3 - 6 (4 bit)
access : read-only
RESERVED1 : reserved for future use
bits : 4 - 8 (5 bit)
access : read-only
FIFO_FULL_RFIFO : Full status indication for Rfifo in manual mode
bits : 5 - 10 (6 bit)
access : read-only
RESERVED2 : reserved for future use
bits : 6 - 12 (7 bit)
access : read-only
FIFO_EMPTY_RFIFO_S : Empty status indication for Rfifo in manual mode
bits : 7 - 14 (8 bit)
access : read-only
FIFO_AEMPTY_RFIFO_S : Aempty status indication for Rfifo in manual mode
bits : 8 - 16 (9 bit)
access : read-only
GSPI_MANUAL_RD_CNT : This is a result of 10 bits ORing counter
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
0 : Disable
No read transactions are in pending
1 : Enable
Read transactions are in pending ( to be done)
End of enumeration elements list.
GSPI_MANUAL_CSN : Provide the status of chip select signal
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
0 : Disable
Active
1 : Enable
Inactive
End of enumeration elements list.
RESERVED3 : reserved for future use
bits : 11 - 42 (32 bit)
access : read-only
GSPI Interrupt Mask Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_INTR_MASK : GSPI Interrupt mask bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
mask the GSPI intr
End of enumeration elements list.
FIFO_AEMPTY_RFIFO_MASK : NONE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
Read fifo almost empty intr mask.
End of enumeration elements list.
FIFO_AFULL_RFIFO_MASK : NONE
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
read fifo almost full intr mask
End of enumeration elements list.
FIFO_AEMPTY_WFIFO_MASK : NONE
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
write fifo almost empty intr mask
End of enumeration elements list.
FIFO_AFULL_WFIFO_MASK : NONE
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
Write fifo almost full intr mask.
End of enumeration elements list.
FIFO_FULL_WFIFO_MASK : NONE
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
write fifo full intr mask.
End of enumeration elements list.
FIFO_EMPTY_RFIFO_MASK : NONE
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
Read fifo is empty intr mask
End of enumeration elements list.
RESERVED1 : reserved for future use
bits : 7 - 38 (32 bit)
access : read-write
GSPI Interrupt Unmask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_INTR_UNMASK : GSPI Interrupt unmask bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
unmask the GSPI intr
End of enumeration elements list.
FIFO_AEMPTY_RFIFO_UNMASK : NONE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
Read fifo almost empty intr unmask.
End of enumeration elements list.
FIFO_AFULL_RFIFO_UNMASK : NONE
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
read fifo almost full intr unmask.
End of enumeration elements list.
FIFO_AEMPTY_WFIFO_UNMASK : NONE
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
write fifo almost empty intr unmask
End of enumeration elements list.
FIFO_AFULL_WFIFO_UNMASK : NONE
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
Write fifo almost full intr unmask.
End of enumeration elements list.
FIFO_FULL_WFIFO_UNMASK : NONE
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
write fifo full intr unmask.
End of enumeration elements list.
FIFO_EMPTY_RFIFO_UNMASK : NONE
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Do not touch
1 : Enable
Read fifo is empty intr unmask
End of enumeration elements list.
RESERVED1 : reserved for future use
bits : 7 - 38 (32 bit)
access : read-write
GSPI Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GSPI_INTR_LVL : GSPI Interrupt status bit
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Disable
no interrupt
1 : Enable
GSPI raised a interrupt
End of enumeration elements list.
FIFO_AEMPTY_RFIFO_LVL : NONE
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : Disable
Read fifo does not reach almost empty threshold.
1 : Enable
Read fifo reached almost empty threshold
End of enumeration elements list.
RESERVED1 : reserved for future use
bits : 2 - 5 (4 bit)
access : read-only
FIFO_AFULL_WFIFO_LVL : NONE
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Disable
Write fifo not reached almost full threshold
1 : Enable
Write fifo almost full threshold
End of enumeration elements list.
FIFO_FULL_WFIFO_LVL : NONE
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : Disable
write fifo not full
1 : Enable
write fifo full
End of enumeration elements list.
FIFO_EMPTY_RFIFO_LVL : NONE
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : Disable
Read fifo is not empty
1 : Enable
Read fifo is empty
End of enumeration elements list.
RESERVED2 : reserved for future use
bits : 7 - 38 (32 bit)
access : read-only
GSPI Interrupt Acknowledge Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GSPI_INTR_ACK : GSPI Interrupt status bit
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : Disable
Do not touch
1 : Enable
GSPI intr ack.
End of enumeration elements list.
FIFO_AEMPTY_RFIFO_ACK : NONE
bits : 1 - 2 (2 bit)
access : write-only
Enumeration:
0 : Disable
Do not touch
1 : Enable
Read fifo almost empty intr ack
End of enumeration elements list.
RESERVED1 : reserved for future use
bits : 2 - 5 (4 bit)
access : write-only
FIFO_AFULL_WFIFO_ACK : NONE
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : Disable
Do not touch
1 : Enable
Write fifo almost full intr ack
End of enumeration elements list.
FIFO_FULL_WFIFO_ACK : NONE
bits : 5 - 10 (6 bit)
access : write-only
Enumeration:
0 : Disable
Do not touch
1 : Enable
write fifo full intr ack
End of enumeration elements list.
FIFO_EMPTY_RFIFO_ACK : NONE
bits : 6 - 12 (7 bit)
access : write-only
Enumeration:
0 : Disable
Do not touch
1 : Enable
Read fifo is empty intr ack
End of enumeration elements list.
RESERVED2 : reserved1
bits : 7 - 38 (32 bit)
access : write-only
GSPI State Machine Monitor Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUS_CTRL_PSTATE : Provides SPI bus controller present state
bits : 0 - 2 (3 bit)
access : read-only
SPI_RD_CNT : number of pending bytes to be read by device
bits : 3 - 18 (16 bit)
access : read-only
RESERVED1 : reserved1
bits : 16 - 47 (32 bit)
access : read-only
GSPI Clock Division Factor Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_CLK_DIV_FACTOR : Provides GSPI clock division factor to the clock divider, which takes SOC clock as input clock and generates required clock according to division factor
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only
GSPI Configuration 3 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SPI_MANUAL_RD_LNTH_TO_BC : Bits are used to indicate the total number of bytes to read from flash during read operation
bits : 0 - 14 (15 bit)
access : read-write
RESERVED1 : reserved1
bits : 15 - 46 (32 bit)
access : read-write
GSPI Bus Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSPI_DATA_SAMPLE_EDGE : Samples MISO data on clock edges. This should be ZERO for mode3 clock
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Pos edge of loop back spi_pad_clk
1 : Enable
Neg edge of loop back spi_pad_clk
End of enumeration elements list.
GSPI_CLK_MODE_CSN0 : NONE
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select0 (csn0)
1 : Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select0 (csn0)
End of enumeration elements list.
GSPI_CLK_MODE_CSN1 : NONE
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select1 (csn1)
1 : Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select1 (csn1)
End of enumeration elements list.
GSPI_CLK_MODE_CSN2 : NONE
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select2 (csn2)
1 : Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select2 (csn2)
End of enumeration elements list.
GSPI_CLK_MODE_CSN3 : NONE
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select3 (csn3)
1 : Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select3 (csn3)
End of enumeration elements list.
GSPI_GPIO_MODE_ENABLES : These bits are used to map GSPI on GPIO pins
bits : 5 - 15 (11 bit)
access : read-write
SPI_HIGH_PERFORMANCE_EN : High performance features are enabled when this bit is set to one
bits : 11 - 22 (12 bit)
access : read-write
RESERVED1 : reserved for future use
bits : 12 - 43 (32 bit)
access : read-write
GSPI fifo
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
GSPI fifo
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRITE_FIFO : FIFO data is write to this address space
bits : 0 - 31 (32 bit)
access : write-only
GSPI READ FIFO
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READ_FIFO : FIFO data is read from this address space
bits : 0 - 31 (32 bit)
access : read-only
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