CTRLR0

SER

BAUDR

TXFTLR

RXFTLR

TXFLR

RXFLR

SR

IMR

ISR

RISR

TXOICR

RXOICR

CTRLR1

RXUICR

MSTICR

ICR

DMACR

DMATDLR

DMARDLR

IDR

SSI_COMP_VERSION

DR

SSIENR

MWCR

RX_SAMPLE_DLY

SPI_CTRLR0

DFS : Select the data frame length (4-bit to 16-bit serial data transfers)
bits : 0 - 3 (4 bit)
access : read-write

FRF : Frame Format, Selects which serial protocol transfers the data
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCPH : Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCPOL : Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMOD : Selects the mode of transfer for serial communication
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLV_OE : DW_apb_ssi is configured as a serial-slave device
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRL : Shift Register Loop Used for testing purposes only
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFS : Control Frame Size Selects the length of the control word for the Micro wire frame format
bits : 12 - 27 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFS_32 : Selects the data frame length
bits : 16 - 36 (21 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI_FRF : Selects data frame format for transmitting or receiving data
bits : 21 - 43 (23 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 23 - 54 (32 bit)
access : read-write

SER : Each bit in this register corresponds to a slave select line (ss_x_n) from the SSI master.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 4 - 35 (32 bit)
access : read-write

SCKDV : SSI Clock Divider.The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register
bits : 0 - 15 (16 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-write

TFT : Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 4 - 35 (32 bit)
access : read-write

RFT : Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 4 - 35 (32 bit)
access : read-write

TXTFL : Contains the number of valid data entries in the transmit FIFO
bits : 0 - 4 (5 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 5 - 36 (32 bit)
access : read-only

RXTFL : Contains the number of valid data entries in the receive FIFO
bits : 0 - 4 (5 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 5 - 36 (32 bit)
access : read-only

BUSY : indicates that a serial transfer is in progress
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TFNF : Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TFE : When the transmit FIFO is completely empty this bit is set
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RFNE : Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RFF : When the receive FIFO is completely full this bit is set
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXE : This bit is cleared when read
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DCOL : This bit is set if the ss_in_n input is asserted by another master, while the ssi master is in the middle of the transfer
bits : 6 - 12 (7 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 7 - 38 (32 bit)
access : read-only

TXEIM : Transmit FIFO Empty Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOIM : Transmit FIFO Overflow Interrupt Mask
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXUIM : Receive FIFO Underflow Interrupt Mask
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOIM : Receive FIFO Overflow Interrupt Mask
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXFIM : Receive FIFO Full Interrupt Mask
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSTIM : Multi-Master Contention Interrupt Mask
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only

TXEIS : Transmit FIFO Empty Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXOIS : Transmit FIFO Overflow Interrupt Status
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXUIS : Receive FIFO Underflow Interrupt Status
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXOIS : Receive FIFO Overflow Interrupt Status
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFIS : Receive FIFO Full Interrupt Status
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MSTIS : Multi-Master Contention Interrupt Status
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only

TXEIR : Transmit FIFO Empty Raw Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXOIR : Transmit FIFO Overflow Raw Interrupt Status
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXUIR : Receive FIFO Underflow Raw Interrupt Status
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXOIR : Receive FIFO Overflow Raw Interrupt Status
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFIR : Receive FIFO Full Raw Interrupt Status
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MSTIR : Multi-Master Contention Raw Interrupt Status
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only

TXOICR : Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt
bits : 0 - 0 (1 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-only

RXOICR : This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt
bits : 0 - 0 (1 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-only

NDF : Number of Data Frames.When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the ssi_master
bits : 0 - 15 (16 bit)
access : read-write

RESERVED1 : Reserved for future use.
bits : 16 - 47 (32 bit)
access : read-write

RXUICR : This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt
bits : 0 - 0 (1 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-only

MSTICR : This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt
bits : 0 - 0 (1 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-only

ICR : This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts
bits : 0 - 0 (1 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-only

RDMAE : This bit enables/disables the receive FIFO DMA channel
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDMAE : This bit enables/disables the transmit FIFO DMA channel
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 2 - 33 (32 bit)
access : read-only

DMATDL : This bit field controls the level at which a DMA request is made by the transmit logic
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 4 - 35 (32 bit)
access : read-only

DMARDL : This bit field controls the level at which a DMA request is made by the receive logic
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 4 - 35 (32 bit)
access : read-write

IDCODE : This register contains the peripherals identification code
bits : 0 - 31 (32 bit)
access : read-only

SSI_COMP_VERSION : Contains the hex representation of the Synopsys component version
bits : 0 - 31 (32 bit)
access : read-only

DR : When writing to this register must right-justify the data
bits : 0 - 31 (32 bit)
access : read-write

SSI_EN : Enables and disables all ssi operations
bits : 0 - 0 (1 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-write

MWMOD : The Micro wire transfer is sequential or non-sequential
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MDD : The direction of the data word when the Micro wire serial protocol is used
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MHS : Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 3 - 34 (32 bit)
access : read-write

RSD : Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input signal.
bits : 0 - 7 (8 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 8 - 39 (32 bit)
access : read-write

TRANS_TYPE : Address and instruction transfer format
bits : 0 - 1 (2 bit)
access : read-write

ADDR_L : This bit defines length of address to be transmitted, The transfer begins only after these many bits are programmed into the FIFO
bits : 2 - 7 (6 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 6 - 13 (8 bit)
access : read-only

INST_L : DUAL/QUAD length in bits
bits : 8 - 17 (10 bit)
access : read-write

RESERVED2 : Reserved for future use
bits : 10 - 20 (11 bit)
access : read-only

WAIT_CYCLES : This bit defines the wait cycles in dual/quad mode between control frames transmit and data reception, Specified as number of SPI clock cycles
bits : 11 - 25 (15 bit)
access : read-write

RESERVED3 : Reserved for future use
bits : 15 - 46 (32 bit)
access : read-only