Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2CC byte (0x0)
mem_usage : registers
protection :
PATTERN_MATCH_MASK_REG_SLICE_0
PATTERN_MATCH_MASK_REG_slice_1
PATTERN_MATCH_MASK_REG_SLICE_2
PATTERN_MATCH_MASK_REG_SLICE_8
PATTERN_MATCH_MASK_REG_SLICE_9
PATTERN_MATCH_MASK_REG_SLICE_10
PATTERN_MATCH_INTR_EN_CLEAR_REG
PATTERN_MATCH_INTR_MASK_SET_REG
PATTERN_MATCH_INTR_MASK_CLEAR_REG
ENABLE REGISTER
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_OPERATION_ENABLE : Contains the Enables for all SIO
bits : 0 - 15 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
GPIO Output enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OEN_VALUE : OEN for the GPIO pins
bits : 0 - 31 (32 bit)
access : read-write
Data Position Counter Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Configuration Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
GPIO Interrupt Enable Set Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_SET : gpio interrupt enable set register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Configuration Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Configuration Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_ENABLE : When set, fifo full indication would be asserted when internal buffer is full
bits : 0 - 0 (1 bit)
access : read-write
EMPTY_ENABLE : When set, fifo full indication would be asserted when internal buffer is empty
bits : 1 - 2 (2 bit)
access : read-write
EDGE_SEL : edge selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
pos edge
1 : Enable
neg edge
End of enumeration elements list.
CLK_SEL : clock selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
internal counter clock is used for shift operations and sent out
1 : Enable
external clock is used for shift operations and is sent out
End of enumeration elements list.
IGNORE_FIRST_SHIFT_CONDITION : data shift condition
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
at a shift/capture happens at the first clock edge
End of enumeration elements list.
FLOW_CONTROL_ENABLED : flow control
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
flow control disable
1 : Enable
flow control enable
End of enumeration elements list.
PATTERN_MATCH_ENABLE : pattern match
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
pattern match disable
1 : Enable
pattern match enable
End of enumeration elements list.
QUALIFIER_MODE : qualifier mode
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : none
Use direct qualifier input
1 : None
Use inverted qualifier
End of enumeration elements list.
QUALIFY_CLOCK : qualify clock
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : none
output clock is not qualified
1 : None
output clock is qualified with qualifier
End of enumeration elements list.
INVERT_CLOCK : invert clock
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : None
direct version of shift clock is provided out
1 : none
inverted version of the clock is provided out
End of enumeration elements list.
PARALLEL_MODE : No. of bits to shift/capture at valid clk edge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00
1 bit
1 : 01
2 bits
2 : 10
4 bits
3 : 11
8 bits
End of enumeration elements list.
PIN_DETECTION_MODE : Pin mode to be considered for gpio interrupt
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00
rise edge
1 : 01
fall edge
2 : 10
level zero
3 : 11
level one
End of enumeration elements list.
SET_CLK_OUT : When high sets the sio clock_out port. This is used only when sio is not enabled
bits : 14 - 28 (15 bit)
access : read-write
RESET_CLK_OUT : When high resets the sio clock_out port. This is used only when sio is not enabled
bits : 15 - 30 (16 bit)
access : read-write
LOAD_DATA_POS_CNTR_VIA_APB : When set, data position counter can be loaded via APB
bits : 16 - 32 (17 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 17 - 48 (32 bit)
access : read-only
Pattern Match Mask Register 0
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_MASK_LOWER16_BITS : Enable for lower 16 bits
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 1
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_MASK_LOWER16_BITS : Enable for lower 16 bits
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 2
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_MASK_LOWER16_BITS : Enable for lower 16 bits
bits : 0 - 31 (32 bit)
access : read-write
GPIO Interrupt Enable Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_CLEAR : gpio interrupt enable Clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
Pattern Match Mask Register Slice 8
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_MASK_LOWER16_BITS : Enable for lower 16 bits
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 9
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_MASK_LOWER16_BITS : Enable for lower 16 bits
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 10
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_MASK_LOWER16_BITS : Enable for lower 16 bits
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 0
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATTERN_MATCH_LOWER16_BITS : Lower 16-bits of pattern to be detected
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 1
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATTERN_MATCH_LOWER16_BITS : Lower 16-bits of pattern to be detected
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 2
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATTERN_MATCH_LOWER16_BITS : Lower 16-bits of pattern to be detected
bits : 0 - 31 (32 bit)
access : read-write
GPIO Interrupt Enable Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_SET : Common gpio interrupt mask set register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Pattern Match Mask Register Slice 8
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATTERN_MATCH_LOWER16_BITS : Lower 16 bits of pattern to be detected
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 9
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATTERN_MATCH_LOWER16_BITS : Lower 16 bits of pattern to be detected
bits : 0 - 31 (32 bit)
access : read-write
Pattern Match Mask Register Slice 10
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATTERN_MATCH_LOWER16_BITS : Lower 16 bits of pattern to be detected
bits : 0 - 31 (32 bit)
access : read-write
Shift Interrupt Enable Set Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_SET : Common shift interrupt enable set register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift Interrupt Enable Clear Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INRT_ENABLE_CLEAR : Common shift interrupt enable Clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
Shift Interrupt Mask Set Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_SET : Common shift interrupt enable Set register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift Interrupt Mask Clear Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_CLEAR : Common shift interrupt mask clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
GPIO Interrupt Enable Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_CLEAR : gpio interrupt mask clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
Shift Interrupt Status Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_SET : Common shift interrupt mask clear register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Swap Interrupt Enable Set Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_SET : Swap interrupt enable set register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Swap Interrupt Enable Clear Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_CLEAR : Swap interrupt enable Clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
Swap Interrupt Mask Set Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_SET : Common swap interrupt mask set register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Swap Interrupt Mask Clear Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_CLEAR : Common swap interrupt mask Clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
Swap Interrupt Statusr Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_SET : Common swap interrupt status register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Pattern Match Interrupt Enable Set Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_ENABLE_SET : Common pattern or buffer under run interrupt enable set register for all SIOs. Each bit corresponds to one SIO
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Pattern Match Interrupt Enable Clear Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INRT_ENABLE_CLEAR : Common pattern or buffer under run interrupt enable clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
Pattern Match Interrupt Mask Set Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_SET : Common pattern or buffer under run interrupt mask set register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Pattern Match Interrupt Mask Clear Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_CLEAR : Common pattern or buffer under run interrupt mask clear register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : write-only
Pattern Match Interrupt Status Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_STATUS : Common pattern interrupt status register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Buffer Interrupt Status Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_STATUS : Common pattern interrupt status register for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
GPIO Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_MASK_SET : Common gpio interrupt status register for all SIOs
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Output muxing Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT_OEN_SEL : OEN select for GPIO pin 0
bits : 0 - 2 (3 bit)
access : read-write
DOUT_SEL : Output mux select for GPIO pin 0
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Shift counter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
Input muxing Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Input clock select for SIO 0
bits : 0 - 2 (3 bit)
access : read-write
QUALIFIER_SELECT : qualifier select
bits : 3 - 7 (5 bit)
access : read-write
QUALIFIER_MODE : qualifier mode
bits : 5 - 11 (7 bit)
access : read-write
DIN_SEL : Data in mux select
bits : 7 - 16 (10 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 10 - 41 (32 bit)
access : read-only
FIFO READ/WRITE Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA_REGISTER : Writes and read into this register will be written into SIO buffer register
bits : 0 - 31 (32 bit)
access : read-write
Points to start slice number forming the FIFO
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_START_SLICE_NUMBER : Points to start slice number forming the FIFO,On write, FIFO_WR_OFFSET_CNT_REG will also be reset to the value pointed written into this register
bits : 0 - 31 (32 bit)
access : read-write
SIO last slice no indication Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_END_SLICE_NUMBER : points to last slice no forming fifo
bits : 0 - 31 (32 bit)
access : read-write
Points to current slice number forming the FIFO
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_CURRENT_SLICE_NUMBER : Next FIFO operation will happen to buffer in the slice pointed by this register
bits : 0 - 31 (32 bit)
access : read-write
Shift counter register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Points to start slice number forming the FIFO
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_START_SLICE_NUMBER : Points to start slice number forming the FIFO
bits : 0 - 31 (32 bit)
access : read-write
Points to last slice number forming the FIFO
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_END_SLICE_NUMBER : Points to last slice number forming the FIFO
bits : 0 - 31 (32 bit)
access : read-write
Points to start current number forming the FIFO
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_CURRENT_SLICE_NUMBER : Next FIFO operation will happen to buffer in the slice pointed by this register This register has to be set to zero before starting fresh DMA operation
bits : 0 - 31 (32 bit)
access : read-write
Shift counter register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
PAUSE REGISTER
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIO_POSITION_COUNTER_DISABLE : Contains sio position counter disable for all SIOs
bits : 0 - 15 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Shift counter register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFT_COUNTER : shift counter current value
bits : 0 - 13 (14 bit)
access : read-only
RESERVED1 : Reserved for future use
bits : 14 - 45 (32 bit)
access : read-only
Buffer Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
GPIO Input Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN_VALUE : GPIO input pin status
bits : 0 - 31 (32 bit)
access : read-only
Buffer Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Buffer Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to load into the shift register
bits : 0 - 31 (32 bit)
access : read-write
Shift counter Reload Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
GPIO Output Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_VALUE : Value to be loaded on GPIO out pins
bits : 0 - 31 (32 bit)
access : read-write
Shift counter Reload Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Shift counter Reload Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : division factor required to generate shift clock
bits : 0 - 13 (14 bit)
access : read-write
RESERVED1 : Reserved for future use
bits : 14 - 28 (15 bit)
access : read-only
REVERSE_LOAD : When set, the data on APB is loaded to buffer is reverse order
bits : 15 - 30 (16 bit)
access : read-write
RESERVED2 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
Data Position Counter Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_VALUE : No. of shifts to happen before reloading the shift register with data/ pausing the operation
bits : 0 - 7 (8 bit)
access : read-write
POSITION_COUNTER : The position counter can be loaded via AHB
bits : 8 - 23 (16 bit)
access : read-write
RESERVED3 : Reserved for future use
bits : 16 - 47 (32 bit)
access : read-only
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