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I2S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

I2S_IER

I2S_LRBR

I2S_LTHR

I2S_CCR

I2S_RCR

I2S_RXFFR

I2S_TCR

I2S_TXFFR

I2S_ISR

I2S_IMR

I2S_RXDMA

I2S_RRXDMA

I2S_TXDMA

I2S_RTXDMA

I2S_COMP_PARAM_2

I2S_COMP_PARAM_1

I2S_COMP_VERSION_REG

I2S_COMP_TYPE_REG

I2S_ROR

I2S_TOR

I2S_RFCR

I2S_TXFCR

I2S_RFF

I2S_TFF

RSVD0

RSVD1

I2S_IRER

I2S_RRBR

I2S_RTHR

I2S_ITER

I2S_RER

I2S_CER

I2S_TER


I2S_IER

I2S Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_IER I2S_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEN RESERVED1

IEN : Inter Block Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable DWP_apb_i2s

1 : Enable

Enable DWP_apb_i2s

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-write


I2S_LRBR

Left Receive Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_LRBR I2S_LRBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LRBR RESERVED1

LRBR : Data received serially from the received channel input
bits : 0 - 23 (24 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 24 - 55 (32 bit)
access : read-only


I2S_LTHR

Left Receive Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LRBR
reset_Mask : 0x0

I2S_LTHR I2S_LTHR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTHR RESERVED1

LTHR : The Left Stereo Data to be transmitted serially from the Transmitted channel output
bits : 0 - 23 (24 bit)
access : write-only

RESERVED1 : Reserved for future use
bits : 24 - 55 (32 bit)
access : write-only


I2S_CCR

Clock Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_CCR I2S_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLKG WSS RESERVED1

SCLKG : These bits are used to program the gating of sclk
bits : 0 - 2 (3 bit)
access : read-write

WSS : These bits are used to program the number of sclk cycles
bits : 3 - 7 (5 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 5 - 36 (32 bit)
access : read-write


I2S_RCR

Receive Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_RCR I2S_RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLEN RESERVED1

WLEN : This Bits are used to program the desired data resolution of the receiver and enables LSB of the incoming left or right word
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : 000

Ignore Word Length

1 : 001

12 Bit Resolution

2 : 010

16 Bit Resolution

3 : 011

20 Bit Resolution

4 : 100

24 Bit Resolution

5 : 101

32 Bit Resolution

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 3 - 34 (32 bit)
access : read-write


I2S_RXFFR

Receiver Block FIFO Reset Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2S_RXFFR I2S_RXFFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFFR RESERVED1

RXFFR : Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit
bits : 0 - 0 (1 bit)
access : write-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : write-only


I2S_TCR

Transmit Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_TCR I2S_TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLEN RESERVED1

WLEN : This Bits are used to program the desired data resolution of the transmitter and ensure that MSB of the data is transmitted first.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : 000

Ignore Word Length

1 : 001

12 Bit Resolution

2 : 010

16 Bit Resolution

3 : 011

20 Bit Resolution

4 : 100

24 Bit Resolution

5 : 101

32 Bit Resolution

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 3 - 34 (32 bit)
access : read-write


I2S_TXFFR

Transmitter Block FIFO Reset Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2S_TXFFR I2S_TXFFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFFR RESERVED1

TXFFR : Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit
bits : 0 - 0 (1 bit)
access : write-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : write-only


I2S_ISR

Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_ISR I2S_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDA RXFO RESERVED1 TXFE TXFO RESERVED2

RXDA : Receive Data Available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

1 : Reached

trigger level reached

0 : Not_reached

trigger level not reached

End of enumeration elements list.

RXFO : Receive Data FIFO
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : Valid

RX FIFO Write valid

1 : Overrun

RX FIFO Write overrun

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 2 - 5 (4 bit)
access : read-only

TXFE : Transmit FIFO Empty
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

1 : Reached

trigger level reached

0 : Not_reached

trigger level not reached

End of enumeration elements list.

TXFO : Transmit FIFO
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : Valid

TX FIFO Write valid

1 : Overrun

TX FIFO Write overrun

End of enumeration elements list.

RESERVED2 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-only


I2S_IMR

Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_IMR I2S_IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDAM RXFOM RESERVED1 TXFEM TXFOM RESERVED2

RXDAM : RX Data Available Mask Interrupt
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : Mask

Mask Interrupt

0 : Unmask

Unmask Interrupt

End of enumeration elements list.

RXFOM : RX FIFO Overrun Mask Interrupt
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : Mask

Mask Interrupt

0 : Unmask

Unmask Interrupt

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 2 - 5 (4 bit)
access : read-write

TXFEM : TX FIFO Empty Interrupt
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : Mask

Mask Interrupt

0 : Unmask

Unmask Interrupt

End of enumeration elements list.

TXFOM : TX FIFO Overrun Interrupt
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : Mask

Mask Interrupt

0 : Unmask

Unmask Interrupt

End of enumeration elements list.

RESERVED2 : Reserved for future use
bits : 6 - 37 (32 bit)
access : read-write


I2S_RXDMA

Receiver Block DMA Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_RXDMA I2S_RXDMA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMA

RXDMA : Used to cycle repeatedly through the enabled receive channels Reading stereo data pairs
bits : 0 - 31 (32 bit)
access : read-only


I2S_RRXDMA

Reset Receiver Block DMA Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2S_RRXDMA I2S_RRXDMA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRXDMA RESERVED1

RRXDMA : Writing a 1 to this self-clearing register resets the RXDMA register
bits : 0 - 0 (1 bit)
access : write-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : write-only


I2S_TXDMA

Transmitter Block DMA Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2S_TXDMA I2S_TXDMA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDMA

TXDMA : Used to cycle repeatedly through the enabled transmit channels allow to writing of stereo data pairs
bits : 0 - 31 (32 bit)
access : write-only


I2S_RTXDMA

Reset Transmitter Block DMA Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2S_RTXDMA I2S_RTXDMA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTXDMA RESERVED1

RTXDMA : Writing a 1 to this self-clearing register resets the TXDMA register
bits : 0 - 0 (1 bit)
access : write-only

RESERVED1 : Reserved1
bits : 1 - 32 (32 bit)
access : write-only


I2S_COMP_PARAM_2

Component Parameter 2 Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_COMP_PARAM_2 I2S_COMP_PARAM_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_RX_WORDSIZE_0 I2S_RX_WORDSIZE_1 RESERVED1

I2S_RX_WORDSIZE_0 : On Read returns the value of word size of receiver channel 0
bits : 0 - 2 (3 bit)
access : read-only

I2S_RX_WORDSIZE_1 : On Read returns the value of word size of receiver channel 1
bits : 3 - 8 (6 bit)
access : read-only

RESERVED1 : Reserved1
bits : 6 - 37 (32 bit)
access : read-only


I2S_COMP_PARAM_1

Component Parameter 1 Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_COMP_PARAM_1 I2S_COMP_PARAM_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB_DATA_WIDTH I2S_FIFO_DEPTH_GLOBAL I2S_FIFO_MODE_EN I2S_TRANSMITTER_BLOCK I2S_RECEIVER_BLOCK I2S_RX_CHANNELS I2S_TX_CHANNELS RESERVED1 I2S_TX_WORDSIZE_0 I2S_TX_WORDSIZE_1 RESERVED2

APB_DATA_WIDTH : Width of APB data bus
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

0 : 0x0

8 Bits

1 : 0x1

16 Bits

2 : 0x2

32 Bits

3 : 0x3

Reserved1

End of enumeration elements list.

I2S_FIFO_DEPTH_GLOBAL : Determines FIFO depth for all channels
bits : 2 - 5 (4 bit)
access : read-only

Enumeration:

0 : 0x0

2 Words deep

1 : 0x1

4 Words deep

2 : 0x2

8 Words deep

3 : 0x3

16 words deep

End of enumeration elements list.

I2S_FIFO_MODE_EN : Determines whether component act as Master or Slave
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

0 : Slave

Mode

1 : Master

Mode

End of enumeration elements list.

I2S_TRANSMITTER_BLOCK : Shows the presence of the transmitter block
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : Absent

Block not present

1 : Present

Block is present

End of enumeration elements list.

I2S_RECEIVER_BLOCK : Shows the presence of the receiver block
bits : 6 - 12 (7 bit)
access : read-only

Enumeration:

0 : Absent

Block not present

1 : Present

Block is present

End of enumeration elements list.

I2S_RX_CHANNELS : Returns the number of receiver channels
bits : 7 - 15 (9 bit)
access : read-only

Enumeration:

0 : 00

1 Channel

1 : 01

2 Channels

2 : 10

3 Channels

3 : 11

4 Channels

End of enumeration elements list.

I2S_TX_CHANNELS : Returns the number of transmitter channels
bits : 9 - 19 (11 bit)
access : read-only

Enumeration:

0 : 00

1 Channel

1 : 01

2 Channels

2 : 10

3 Channels

3 : 11

4 Channels

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 11 - 26 (16 bit)
access : read-only

I2S_TX_WORDSIZE_0 : Returns the value of word size of transmitter channel 0
bits : 16 - 34 (19 bit)
access : read-only

I2S_TX_WORDSIZE_1 : Returns the value of word size of transmitter channel 1
bits : 19 - 40 (22 bit)
access : read-only

RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only


I2S_COMP_VERSION_REG

Component Version ID
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_COMP_VERSION_REG I2S_COMP_VERSION_REG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_COMP_VERSION

I2S_COMP_VERSION : Return the component version(1.02)
bits : 0 - 31 (32 bit)
access : read-only


I2S_COMP_TYPE_REG

Component Type
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_COMP_TYPE_REG I2S_COMP_TYPE_REG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_COMP_TYPE

I2S_COMP_TYPE : Return the component type
bits : 0 - 31 (32 bit)
access : read-only


I2S_ROR

Receive Overrun Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_ROR I2S_ROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHO RESERVED1

RXCHO : Read this bit to clear the RX FIFO data overrun interrupt
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

1 : Overrun

RX FIFO Write Overrun

0 : Valid

RX FIFO Write Valid

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-only


I2S_TOR

Transmit Overrun Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_TOR I2S_TOR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHO RESERVED1

TXCHO : Read this bit to clear the TX FIFO data overrun interrupt
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

1 : Overrun

TX FIFO Write Overrun

0 : Valid

TX FIFO Write Valid

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-only


I2S_RFCR

Receive FIFO Configuration Register0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_RFCR I2S_RFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHDT RESERVED1

RXCHDT : This bits program the trigger level in the RX FIFO at which the data available interrupt is generated
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 4 - 35 (32 bit)
access : read-write


I2S_TXFCR

Transmit FIFO Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_TXFCR I2S_TXFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHET RESERVED1

TXCHET : This bits program the trigger level in the TX FIFO at which the Empty Threshold Reached interrupt is generated
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved for future use
bits : 4 - 35 (32 bit)
access : read-only


I2S_RFF

Receive FIFO Flush
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2S_RFF I2S_RFF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHFR RESERVED1

RXCHFR : Writing a 1 to this register flushes an individual RX FIFO RX channel or block must be disable prior to writing to this bit
bits : 0 - 0 (1 bit)
access : write-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : write-only


I2S_TFF

Transmit FIFO Flush
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2S_TFF I2S_TFF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHFR RESERVED1

TXCHFR : Writing a 1 to this register flushes an individual TX FIFO TX channel or block must be disable prior to writing to this bit
bits : 0 - 0 (1 bit)
access : write-only

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : write-only


RSVD0

none
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSVD0 RSVD0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD1

none
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSVD1 RSVD1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2S_IRER

I2S Receiver Block Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_IRER I2S_IRER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN RESERVED1

RXEN : Receive Block Enable, Bit Overrides any Individual Receive Channel Enables
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable Receiver

1 : Enable

Enable Receiver

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-write


I2S_RRBR

Right Receive Buffer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2S_RRBR I2S_RRBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRBR RESERVED1

RRBR : The Right Stereo Data received serially from the received channel input through this register
bits : 0 - 23 (24 bit)
access : read-only

RESERVED1 : Reserved for future use
bits : 24 - 55 (32 bit)
access : read-only


I2S_RTHR

Right Transmit Holding Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : RRBR
reset_Mask : 0x0

I2S_RTHR I2S_RTHR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTHR RESERVED1

RTHR : The Right Stereo Data to be transmitted serially from the Transmit channel output written through this register
bits : 0 - 23 (24 bit)
access : write-only

RESERVED1 : Reserved for future use
bits : 24 - 55 (32 bit)
access : write-only


I2S_ITER

Transmitter Block Enable
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_ITER I2S_ITER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEN RESERVED1

TXEN : Transmitter Block Enable, Bit Overrides any Individual Transmit Channel Enables
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Transmit channel is disabled

1 : Enable

Transmit channel is enabled

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-write


I2S_RER

Receive Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_RER I2S_RER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHEN RESERVED1

RXCHEN : This Bit enables/disables a receive channel independently of all other channels
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Receive Channel is Disable

1 : Enable

Receive Channel is Disable

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-write


I2S_CER

Clock Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_CER I2S_CER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKEN RESERVED1

CLKEN : Clock generation enable/disable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

none

1 : Enable

none

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-write


I2S_TER

Transmit Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2S_TER I2S_TER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHEN RESERVED1

TXCHEN : This Bit enables/disables a transmit channel independently of all other channels
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Transmit Channel is Disable

1 : Enable

Transmit Channel is Enable

End of enumeration elements list.

RESERVED1 : Reserved for future use
bits : 1 - 32 (32 bit)
access : read-write



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