\n
address_offset : 0x0 Bytes (0x0)
size : 0xB0 byte (0x0)
mem_usage : registers
protection :
General control set register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_IN_32_BIT_MODE : Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1 : Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
End of enumeration elements list.
SOFT_RESET_COUNTER_0_FRM_REG : This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read: Always should return 0
1 : Enable
If Write: Counter_1 will be reset If Read: Always should return 0
End of enumeration elements list.
PERIODIC_EN_COUNTER_0_FRM_REG : This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
1 : Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
End of enumeration elements list.
COUNTER_0_TRIG_FRM_REG : This enables the counter to run/active
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Read should always return 0
1 : Enable
If Write:Counter_1 will be active If Read:Read should always return 0
End of enumeration elements list.
COUNTER_0_UP_DOWN : This enables the counter to run in up/down/up-down/down-up directions
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : 00
If Write:No effect If Read:Counter_0 is in down-up counting mode
1 : 01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
2 : 10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
3 : 11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
End of enumeration elements list.
COUNTER_0_SYNC_TRIG : This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Read should always return 0
1 : Enable
If Write:Counter_0 will be active. If Read:Read should always return 0
End of enumeration elements list.
BUF_REG_0_EN : Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
1 : Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 8 - 24 (17 bit)
access : read-write
SOFT_RESET_COUNTER_1_FRM_REG : This resets the counter on the write
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
If Write:No effect If Read:Always should return 0
1 : Enable
If Write:Counter_1 will be reset If Read:Always should return 0
End of enumeration elements list.
PERIODIC_EN_COUNTER_1_FRM_REG : This resets the counter on the write
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
1 : Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
End of enumeration elements list.
COUNTER_1_TRIG_FRM : This enables the counter to run/active
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
If Write:No effect If Read:Always should return 0
1 : Enable
If Write:Counter_1 will be active If Read:Always should return 0
End of enumeration elements list.
COUNTER_1_UP_DOWN : This enables the counter to run in upward direction
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : 00
If Write:No effect If Read:Counter_1 is in down-up counting mode
1 : 01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
2 : 10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
3 : 11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
End of enumeration elements list.
COUNTER_1_SYNC_TRIG : This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Read should always return 0
1 : Enable
If Write:Counter_1 will be active. If Read:Read should always return 0
End of enumeration elements list.
BUF_REG_1_EN : Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
1 : Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 24 - 55 (32 bit)
access : read-write
Interrupts unmask
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_0_L : Interrupt unmask signal.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
FIFO_0_FULL_L : Interrupt unmask signal.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_0_IS_ZERO_L : Interrupt unmask signal.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_0_IS_PEAK_L : Interrupt unmask signal.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 4 - 19 (16 bit)
access : read-only
INTR_1_L : Interrupt unmask signal.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
FIFO_1_FULL_L : Interrupt unmask signal
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_1_IS_ZERO_L : Interrupt unmask signal.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_1_IS_PEAK_L : Interrupt unmask signal.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 20 - 51 (32 bit)
access : read-only
Interrupt clear/ack register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_0_L : Interrupt ack signal.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
FIFO_0_FULL_L : Interrupt ack signal.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
COUNTER_0_IS_ZERO_L : Interrupt ack signal.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
COUNTER_0_IS_PEAK_L : Interrupt ack signal.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 4 - 19 (16 bit)
access : read-only
INTR_1_L : Interrupt ack signal.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
FIFO_1_FULL_L : Interrupt ack signal.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
COUNTER_1_IS_ZERO_L : Interrupt ack signal.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
COUNTER_1_IS_PEAK_L : Interrupt ack signal.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect. If Read: should be returned as this is self clear bit
1 : Enable
If Write: Interrupt will be de asserted.
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 20 - 51 (32 bit)
access : read-write
Match value register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_0_MATCH : This will be used as lower match
bits : 0 - 15 (16 bit)
access : read-write
COUNTER_1_MATCH : This will be used as upper match
bits : 16 - 47 (32 bit)
access : read-write
Match Buffer register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_0_MATCH_BUF : This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0.
bits : 0 - 15 (16 bit)
access : read-write
COUNTER_1_MATCH_BUF : This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0.
bits : 16 - 47 (32 bit)
access : read-write
Capture Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
COUNTER_0_CAPTURE : This is a latched value of counter lower part when the selected capture_event occurs
bits : 0 - 15 (16 bit)
access : read-only
COUNTER_1_CAPTURE : This is a latched value of counter upper part when the selected capture_event occurs
bits : 16 - 47 (32 bit)
access : read-only
Counter Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
COUNTER0 : This holds the value of counter-0
bits : 0 - 15 (16 bit)
access : read-only
COUNTER1 : This holds the value of counter-1
bits : 16 - 47 (32 bit)
access : read-only
OCU control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT_IS_OCU_0 : Indicates whether the output is in OCU mode or not for channel-0
bits : 0 - 0 (1 bit)
access : read-write
SYNC_WITH_0 : Indicates whether the other channel is in sync with this channel
bits : 1 - 4 (4 bit)
access : read-write
OCU_0_DMA_MODE : Indicates whether the OCU DMA mode is active or not for channel 0
bits : 4 - 8 (5 bit)
access : read-write
OCU_0_MODE_8_16 : Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode
bits : 5 - 10 (6 bit)
access : read-write
MAKE_OUTPUT_0_HIGH_SEL : Check counter ocus for possibilities. When this is hit output will be made high.
bits : 6 - 14 (9 bit)
access : read-write
MAKE_OUTPUT_0_LOW_SEL : Check counter ocus for possibilities. When this is hit output will be made low.
bits : 9 - 20 (12 bit)
access : read-write
RESERVED1 : Reserved1
bits : 12 - 27 (16 bit)
access : read-write
OUTPUT_1_IS_OCU : Indicates whether the output is in OCU mode or not for channel 1
bits : 16 - 32 (17 bit)
access : read-write
SYNC_WITH_1 : Indicates whether the other channel is in sync with this channel
bits : 17 - 36 (20 bit)
access : read-write
OCU_1_DMA_MODE : Indicates whether the OCU DMA mode is active or not for channel 1
bits : 20 - 40 (21 bit)
access : read-write
OCU_1_MODE_8_16_MODE : Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode
bits : 21 - 42 (22 bit)
access : read-write
MAKE_OUTPUT_1_HIGH_SEL : Check counter ocus for possibilities. When this is hit output will be made high.
bits : 22 - 46 (25 bit)
access : read-write
MAKE_OUTPUT_1_LOW_SEL : Check counter ocus for possibilities. When this is hit output will be made low.
bits : 25 - 52 (28 bit)
access : read-write
RESERVED2 : Reserved2
bits : 28 - 59 (32 bit)
access : read-write
OCU Compare Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU_COMPARE_0_REG : Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
bits : 0 - 15 (16 bit)
access : read-write
OCU_COMPARE_1_REG : Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
bits : 16 - 47 (32 bit)
access : read-write
OCU Compare2 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU_COMPARE2_0_REG : Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
bits : 0 - 15 (16 bit)
access : read-write
OCU_COMPARE2_1_REG : Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
bits : 16 - 47 (32 bit)
access : read-write
OCU Synchronization Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU_SYNC_CHANNEL0_REG : Starting point of channel 0 for synchronization purpose
bits : 0 - 15 (16 bit)
access : read-write
OCU_SYNC_CHANNEL1_REG : Starting point of channel 1 for synchronization purpose
bits : 16 - 47 (32 bit)
access : read-write
PWM compare next register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU_COMPARE_NXT_COUNTER1 : OCU output should be high for counter 1
bits : 0 - 15 (16 bit)
access : read-write
OCU_COMPARE_NXT_COUNTER0 : PWM output should be high for counter 0
bits : 16 - 47 (32 bit)
access : read-write
WFG control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAKE_OUTPUT_0_TGL_0_SEL : Check the counter ocus possibilities for description for channel 0.
bits : 0 - 2 (3 bit)
access : read-write
MAKE_OUTPUT_0_TGL_1_SEL : Check the counter ocus possibilities for description for channel 0.
bits : 3 - 8 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 13 (8 bit)
access : read-write
WFG_TGL_CNT_0_PEAK : WFG mode output toggle count clock for channel 0.
bits : 8 - 23 (16 bit)
access : read-write
MAKE_OUTPUT_1_TGL_0_SEL : Check the counter ocus possibilities for description for channel 1.
bits : 16 - 34 (19 bit)
access : read-write
MAKE_OUTPUT_1_TGL_1_SEL : Check the counter ocus possibilities for description for channel 1.
bits : 19 - 40 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 45 (24 bit)
access : read-write
WFG_TGL_CNT_1_PEAK : WFG mode output toggle count clock for channel 1
bits : 24 - 55 (32 bit)
access : read-write
General control reset register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_IN_32_BIT_MODE : Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1 : Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 1 - 2 (2 bit)
access : read-only
PERIODIC_EN_COUNTER_0_FRM_REG : This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
1 : Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 3 - 6 (4 bit)
access : read-only
COUNTER_0_UP_DOWN : This enables the counter to run in up/down/up-down/down-up directions
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : 00
If Write:No effect If Read:Counter_0 is in down-up counting mode
1 : 01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
2 : 10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
3 : 11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
End of enumeration elements list.
RESERVED3 : Reserved3
bits : 6 - 12 (7 bit)
access : read-only
BUF_REG_0_EN : Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
1 : Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
End of enumeration elements list.
RESERVED4 : Reserved4
bits : 8 - 24 (17 bit)
access : read-only
RESERVED5 : Reserved5
bits : 17 - 34 (18 bit)
access : read-only
PERIODIC_EN_COUNTER_1_FRM_REG : This resets the counter on the write
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
1 : Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
End of enumeration elements list.
RESERVED6 : Reserved6
bits : 19 - 38 (20 bit)
access : read-only
COUNTER_1_UP_DOWN : This enables the counter to run in upward direction
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : 00
If Write:No effect If Read:Counter_1 is in down-up counting mode
1 : 01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
2 : 10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
3 : 11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
End of enumeration elements list.
RESERVED7 : Reserved7
bits : 22 - 44 (23 bit)
access : read-only
BUF_REG_1_EN : Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
1 : Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
End of enumeration elements list.
RESERVED8 : Reserved8
bits : 24 - 55 (32 bit)
access : read-only
PWM compare next register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCU_COMPARE2_NXT_COUNTER0 : OCU output should be high for counter 1
bits : 0 - 15 (16 bit)
access : read-write
OCU_COMPARE2_NXT_COUNTER1 : PWM output should be high for counter 0
bits : 16 - 47 (32 bit)
access : read-write
Start counter event select register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START_COUNTER_0_EVENT_SEL : For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 21 (16 bit)
access : read-write
START_COUNTER_1_EVENT_SEL : For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description
bits : 16 - 37 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only
Start counter AND event register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START_COUNTER_0_AND_EVENT : For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
START_COUNTER_0_AND_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
START_COUNTER_1_AND_EVENT : For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
START_COUNTER_1_AND_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Start counter OR event register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START_COUNTER_0_OR_EVENT : For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
START_COUNTER_0_OR_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write
START_COUNTER_1_OR_EVENT : For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid.
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
START_COUNTER_1_OR_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Continue counter event select register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONTINUE_COUNTER_0_EVENT_SEL : For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 21 (16 bit)
access : read-write
CONTINUE_COUNTER_1_EVENT_SEL : For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid.
bits : 16 - 37 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only
Continue counter AND event register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONTINUE_COUNTER_0_AND_EVENT : For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event.
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
CONTINUE_COUNTER_0_AND_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write
CONTINUE_COUNTER_1_AND_EVENT : For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
CONTINUE_COUNTER_1_AND_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Continue counter OR event register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONTINUE_COUNTER_0_OR_EVENT : For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
CONTINUE_COUNTER_0_OR_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write
CONTINUE_COUNTER_1_OR_EVENT : For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
CONTINUE_COUNTER_1_OR_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Stop counter event select register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP_COUNTER_0_EVENT_SEL : For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 21 (16 bit)
access : read-write
STOP_COUNTER_1_EVENT_SEL : For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid
bits : 16 - 37 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only
Stop counter AND event register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP_COUNTER_0_AND_EVENT : For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
STOP_COUNTER_0_AND_VLD : Indicates which bits in 3:0 are valid for considering AND event
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write
STOP_COUNTER_1_AND_EVENT : For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
STOP_COUNTER_1_AND_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Stop counter OR event register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP_COUNTER_0_OR_EVENT : For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
STOP_COUNTER_0_OR_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write
STOP_COUNTER_1_OR_EVENT : For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
STOP_COUNTER_1_OR_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Halt counter event select register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALT_COUNTER_0_EVENT_SEL : For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
bits : 0 - 5 (6 bit)
access : read-write
RESUME_FROM_HALT_COUNTER_0 : For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
bits : 6 - 12 (7 bit)
access : write-only
RESERVED1 : Reserved1
bits : 7 - 22 (16 bit)
access : read-only
HALT_COUNTER_1_EVENT_SEL : For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid
bits : 16 - 37 (22 bit)
access : read-write
RESUME_FROM_HALT_COUNTER_1 : For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
bits : 22 - 44 (23 bit)
access : write-only
RESERVED2 : Reserved2
bits : 23 - 54 (32 bit)
access : read-only
Halt counter AND event register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALT_COUNTER_0_AND_EVENT : For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
HALT_COUNTER_0_AND_VLD : Indicates which bits in 3:0 are valid for considering AND event
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
HALT_COUNTER_1_AND_EVENT : For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
HALT_COUNTER_1_AND_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Halt counter OR event register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALT_COUNTER_0_OR_EVENT : For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
HALT_COUNTER_0_OR_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
HALT_COUNTER_1_OR_EVENT : For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
HALT_COUNTER_1_OR_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Interrupt status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
INTR_0_L : Indicates the FIFO full signal of channel-0
bits : 0 - 0 (1 bit)
access : read-only
FIFO_0_FULL_L : Indicates the FIFO full signal of channel-0
bits : 1 - 2 (2 bit)
access : read-only
COUNTER_0_IS_ZERO_L : Counter 0 hit zero in active mode.
bits : 2 - 4 (3 bit)
access : read-only
COUNTER_0_IS_PEAK_L : Counter 0 hit peak (MATCH) in active mode.
bits : 3 - 6 (4 bit)
access : read-only
RESERVED1 : Reserved1
bits : 4 - 19 (16 bit)
access : read-only
INTR_1_L : Indicates the FIFO full signal of channel-1
bits : 16 - 32 (17 bit)
access : read-only
FIFO_1_FULL_L : Indicates the FIFO full signal of channel-1
bits : 17 - 34 (18 bit)
access : read-only
COUNTER_1_IS_ZERO_L : Counter 1 hit zero in active mode.
bits : 18 - 36 (19 bit)
access : read-only
COUNTER_1_IS_PEAK_L : Counter 1 hit peak (MATCH) in active mode.
bits : 19 - 38 (20 bit)
access : read-only
RESERVED2 : Reserved2
bits : 20 - 51 (32 bit)
access : read-only
Increment counter event select register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_COUNTER_0_EVENT_SEL : For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 21 (16 bit)
access : read-only
INCREMENT_COUNTER_1_EVENT_SEL : For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid
bits : 16 - 37 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only
Increment counter AND event register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_COUNTER_0_AND_EVENT : For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
INCREMENT_COUNTER_0_AND_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
INCREMENT_COUNTER_1_AND_EVENT : For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
INCREMENT_COUNTER_1_AND_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Increment counter OR event register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_COUNTER_0_OR_EVENT : For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
INCREMENT_COUNTER_0_OR_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
INCREMENT_COUNTER_1_OR_EVENT : For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED4 : Reserved4
bits : 20 - 43 (24 bit)
access : read-only
INCREMENT_COUNTER_1_OR_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED5 : Reserved5
bits : 28 - 59 (32 bit)
access : read-only
Capture counter event select register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_COUNTER_0_EVENT_SEL : For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 21 (16 bit)
access : read-only
CAPTURE_COUNTER_1_EVENT_SEL : For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid
bits : 16 - 37 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only
Capture counter AND event register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_COUNTER_0_AND_EVENT : For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
CAPTURE_COUNTER_0_AND_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
CAPTURE_COUNTER_1_AND_EVENT : For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
CAPTURE_COUNTER_1_AND_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Capture counter OR event register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_COUNTER_0_OR_EVENT : For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
CAPTURE_COUNTER_0_OR_VLD : none
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
CAPTURE_COUNTER_1_OR_EVENT : For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
CAPTURE_COUNTER_1_OR_VLD : none
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Output event select register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT_EVENT_SEL_0 : For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 21 (16 bit)
access : read-only
OUTPUT_EVENT_SEL_1 : For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid
bits : 16 - 37 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only
Output AND event Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT_0_AND_EVENT : AND expression for AND event in output Counter_0 event.
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
OUTPUT_0_AND_VLD : AND expression for AND event in output Counter_0 event.
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
OUTPUT_1_AND_EVENT : AND expression for AND event in output Counter_1 event.
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
OUTPUT_1_AND_VLD : AND expression for AND event in output Counter_1 event.
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Output OR event Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT_0_OR_EVENT : OR expression for OR event in output Counter_0 event
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
OUTPUT_0_OR_VLD : Indicates which bits in 3:0 are valid for considering OR event
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
OUTPUT_1_OR_EVENT : OR expression for OR event in output Counter_0 event
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
OUTPUT_1_OR_VLD : Indicates which bits in 3:0 are valid for considering OR event
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Interrupt Event Select Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_EVENT_SEL_0 : For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event
bits : 0 - 5 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 21 (16 bit)
access : read-only
INTR_EVENT_SEL_1 : For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid
bits : 16 - 37 (22 bit)
access : read-write
RESERVED2 : Reserved2
bits : 22 - 53 (32 bit)
access : read-only
Interrupt AND Event Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_0_AND_EVENT : None
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
INTR_0_AND_VLD : None
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
INTR_1_AND_EVENT : None
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
INTR_1_AND_VLD : None
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Interrupt OR Event Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_0_OR_EVENT : None
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write
INTR_0_OR_VLD : None
bits : 8 - 19 (12 bit)
access : read-write
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-only
INTR_1_OR_EVENT : None
bits : 16 - 35 (20 bit)
access : read-write
RESERVED3 : Reserved3
bits : 20 - 43 (24 bit)
access : read-only
INTR_1_OR_VLD : None
bits : 24 - 51 (28 bit)
access : read-write
RESERVED4 : Reserved4
bits : 28 - 59 (32 bit)
access : read-only
Interrupts mask
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR_0_L : Interrupt mask signal.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
FIFO_0_FULL_L : Interrupt mask signal.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_0_IS_ZERO_L : Interrupt mask signal.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_0_IS_PEAK_L : Interrupt mask signal.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 4 - 19 (16 bit)
access : read-write
INTR_1_L : Interrupt mask signal.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
FIFO_1_FULL_L : Interrupt mask signal.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_1_IS_ZERO_L : Interrupt mask signal.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
COUNTER_1_IS_PEAK_L : Interrupt mask signal.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
If Write: No effect If Read:Interrupt is masked.
1 : Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 20 - 51 (32 bit)
access : read-write
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