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CT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

CT_MUX_SEL_0_REG

CT_OUTPUT_EVENT1_ADC_SEL

CT_OUTPUT_EVENT2_ADC_SEL

CT_MUX_SEL_1_REG

CT_MUX_SEL_2_REG

CT_MUX_SEL_3_REG


CT_MUX_SEL_0_REG

MUX_SEL_0_REG Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CT_MUX_SEL_0_REG CT_MUX_SEL_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUX_SEL_0 RESERVED1

MUX_SEL_0 : Select value to select first output value fifo_0_full[0] out of all the fifo_0_full_muxed signals of counter 0
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write


CT_OUTPUT_EVENT1_ADC_SEL

OUTPUT_EVENT_ADC_SEL Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CT_OUTPUT_EVENT1_ADC_SEL CT_OUTPUT_EVENT1_ADC_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTPUT_EVENT_ADC_SEL RESERVED1

OUTPUT_EVENT_ADC_SEL : Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write


CT_OUTPUT_EVENT2_ADC_SEL

OUTPUT_EVENT_ADC_SEL Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CT_OUTPUT_EVENT2_ADC_SEL CT_OUTPUT_EVENT2_ADC_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTPUT_EVENT_ADC_SEL RESERVED1

OUTPUT_EVENT_ADC_SEL : Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write


CT_MUX_SEL_1_REG

MUX_SEL_1_REG Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CT_MUX_SEL_1_REG CT_MUX_SEL_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUX_SEL_1 RESERVED1

MUX_SEL_1 : Select value to select first output value fifo_0_full[1] out of all the fifo_0_full_muxed signals of counter 0
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write


CT_MUX_SEL_2_REG

MUX_SEL_2_REG Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CT_MUX_SEL_2_REG CT_MUX_SEL_2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUX_SEL_2 RESERVED1

MUX_SEL_2 : Select value to select first output value fifo_1_full[0] out of all the fifo_1_full_muxed signals of counter 1
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write


CT_MUX_SEL_3_REG

MUX_SEL_3_REG Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CT_MUX_SEL_3_REG CT_MUX_SEL_3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUX_SEL_3 RESERVED1

MUX_SEL_3 : Select value to select first output value fifo_1_full[1] out of all the fifo_1_full_muxed signals of counter 1
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write



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