\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
MUX_SEL_0_REG Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_SEL_0 : Select value to select first output value fifo_0_full[0] out of all the fifo_0_full_muxed signals of counter 0
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write
OUTPUT_EVENT_ADC_SEL Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT_EVENT_ADC_SEL : Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write
OUTPUT_EVENT_ADC_SEL Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT_EVENT_ADC_SEL : Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write
MUX_SEL_1_REG Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_SEL_1 : Select value to select first output value fifo_0_full[1] out of all the fifo_0_full_muxed signals of counter 0
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write
MUX_SEL_2_REG Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_SEL_2 : Select value to select first output value fifo_1_full[0] out of all the fifo_1_full_muxed signals of counter 1
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write
MUX_SEL_3_REG Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_SEL_3 : Select value to select first output value fifo_1_full[1] out of all the fifo_1_full_muxed signals of counter 1
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 35 (32 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.