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EGPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1260 byte (0x0)
mem_usage : registers
protection :

Registers

GPIO_CONFIG_REG

PORT_LOAD_REG

GPIO_INTR_CTRL

GPIO_GRP_INTR_CTRL_REG

PORT_TOGGLE_REG

PORT_READ_REG

BIT_LOAD_REG

PORT_SET_REG

GPIO_INTR_STATUS

GPIO_GRP_INTR_STS

WORD_LOAD_REG

PORT_CLEAR_REG

PORT_MASKED_LOAD_REG


GPIO_CONFIG_REG

GPIO Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_CONFIG_REG GPIO_CONFIG_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIRECTION PORTMASK MODE RESERVED1 GROUP_INTERRUPT1_ENABLE GROUP_INTERRUPT1_POLARITY GROUP_INTERRUPT2_ENABLE GROUP_INTERRUPT2_POLARITY RESERVED2 RESERVED3

DIRECTION : Direction of the GPIO pin
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Output

1 : Enable

Input

End of enumeration elements list.

PORTMASK : Port mask value
bits : 1 - 2 (2 bit)
access : read-write

MODE : GPIO Pin Mode Used for GPIO Pin Muxing
bits : 2 - 7 (6 bit)
access : read-write

Enumeration:

0 : Mode0

000: Mode 0

1 : Mode1

001:Mode 1

2 : Mode2

010:Mode 2

3 : Mode3

011:Mode 3

4 : Mode4

100:Mode 4

5 : Mode5

101: Mode 5

6 : Mode6

110:Mode 6

7 : Mode7

111:Mode 7

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 6 - 13 (8 bit)
access : read-write

GROUP_INTERRUPT1_ENABLE : When set, the corresponding GPIO is pin is selected for group intr 1 generation
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : Enable

enable the gpio group interrupt

0 : Disable

disable the gpio group interrupt1

End of enumeration elements list.

GROUP_INTERRUPT1_POLARITY : Decides the active value of the pin to be considered for group interrupt 1 generation
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : Disable

group interrupt gets generated when gpio input pin status is zero

1 : Enable

grp interrupt gets generated when gpio input pin status is 1

End of enumeration elements list.

GROUP_INTERRUPT2_ENABLE : When set, the corresponding GPIO is pin is selected for group intr 2 generation
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : Enable

enable the gpio group interrupt2

0 : Disable

disable the gpio group interrupt2

End of enumeration elements list.

GROUP_INTERRUPT2_POLARITY : Decides the active value of the pin to be considered for group interrupt 2 generation
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : Disable

group interrupt gets generated when gpio input pin status is zero

1 : Enable

grp interrupt gets generated when gpio input pin status is 1

End of enumeration elements list.

RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write

RESERVED3 : Reserved3
bits : 16 - 47 (32 bit)
access : read-write


PORT_LOAD_REG

Port Load
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORT_LOAD_REG PORT_LOAD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_LOAD RES

PORT_LOAD : Loads the value on to pin on write. And reads the value of load register on read
bits : 0 - 15 (16 bit)
access : read-write

RES : RES
bits : 16 - 47 (32 bit)
access : read-only


GPIO_INTR_CTRL

GPIO Interrupt Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_INTR_CTRL GPIO_INTR_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEVEL_HIGH_ENABLE LEVEL_LOW_ENABLE RISE_EDGE_ENABLE FALL_EDGE_ENABLE MASK RESERVED1 PIN_NUMBER PORT_NUMBER RESERVED2

LEVEL_HIGH_ENABLE : enables interrupt generation when pin level is 1
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

disabled

1 : Enable

Interrupt enabled

End of enumeration elements list.

LEVEL_LOW_ENABLE : enables interrupt generation when pin level is 0
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

disabled

1 : Enable

Interrupt enabled

End of enumeration elements list.

RISE_EDGE_ENABLE : enables interrupt generation when rising edge is detected on pin
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

disabled

1 : Enable

Interrupt enabled

End of enumeration elements list.

FALL_EDGE_ENABLE : enables interrupt generation when Falling edge is detected on pin
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

disabled

1 : Enable

Interrupt enabled

End of enumeration elements list.

MASK : Masks the interrupt. Interrupt will still be seen in status register when enabled
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Interrupt masked

1 : Enable

Interrupt unmasked

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 5 - 12 (8 bit)
access : read-write

PIN_NUMBER : GPIO Pin to be chosen for interrupt generation
bits : 8 - 19 (12 bit)
access : read-write

PORT_NUMBER : GPIO Port to be chosen for interrupt generation
bits : 12 - 25 (14 bit)
access : read-write

RESERVED2 : Reserved2
bits : 14 - 45 (32 bit)
access : read-write


GPIO_GRP_INTR_CTRL_REG

GPIO Interrupt 0 Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_GRP_INTR_CTRL_REG GPIO_GRP_INTR_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AND_OR LEVEL_EDGE ENABLE_WAKEUP ENABLE_INTERRUPT MASK RESERVED1

AND_OR : AND/OR
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

AND

1 : Enable

OR

End of enumeration elements list.

LEVEL_EDGE : Level/Edge
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Level

1 : Enable

Edge

End of enumeration elements list.

ENABLE_WAKEUP : For wakeup generation, actual pin status has to be seen(before double ranking point)
bits : 2 - 4 (3 bit)
access : read-write

ENABLE_INTERRUPT : Enable Interrupt
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

MASK : Mask
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Mask

1 : Enable

unmask

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 5 - 36 (32 bit)
access : read-write


PORT_TOGGLE_REG

Port Toggle Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_TOGGLE_REG PORT_TOGGLE_REG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_TOGGLE RESERVED1

PORT_TOGGLE : Toggles the pin when corresponding bit is high. Writing zero has not effect.
bits : 0 - 15 (16 bit)
access : write-only

RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only


PORT_READ_REG

Port Read Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PORT_READ_REG PORT_READ_REG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_READ RESERVED1

PORT_READ : Reads the value on GPIO pins irrespective of the pin mode.
bits : 0 - 15 (16 bit)
access : read-only

RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-only


BIT_LOAD_REG

Bit Load
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BIT_LOAD_REG BIT_LOAD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT_LOAD RESERVED1

BIT_LOAD : Loads 0th bit on to the pin on write. And reads the value on pin on read into 0th bit
bits : 0 - 0 (1 bit)
access : read-write

RESERVED1 : Reserved1
bits : 1 - 32 (32 bit)
access : read-write


PORT_SET_REG

Port Set Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_SET_REG PORT_SET_REG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_SET RESERVED1

PORT_SET : Sets the pin when corresponding bit is high. Writing zero has no effect.
bits : 0 - 15 (16 bit)
access : write-only

RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only


GPIO_INTR_STATUS

GPIO Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_INTR_STATUS GPIO_INTR_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_STATUS RISE_EDGE_STATUS FALL_EDGE_STATUS MASK_SET MASK_CLEAR RESERVED1

INTERRUPT_STATUS : Gets set when interrupt is enabled and occurs.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Writing 0 has not effect

1 : Enable

When 1 is written it gets cleared. Also clears rise edge and fall edge status bits

End of enumeration elements list.

RISE_EDGE_STATUS : Gets set when rise edge is enabled and occurs.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Writing 0 has not effect

1 : Enable

When 1 is written it gets cleared.

End of enumeration elements list.

FALL_EDGE_STATUS : Gets set when Fall edge is enabled and occurs.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Writing 0 has not effect

1 : Enable

When 1 is written it gets cleared.

End of enumeration elements list.

MASK_SET : Mask set
bits : 3 - 6 (4 bit)
access : write-only

Enumeration:

0 : Disable

On read, this bit should result it in 0

1 : Enable

When 1 is written mask bit will get set

End of enumeration elements list.

MASK_CLEAR : Mask Clear
bits : 4 - 8 (5 bit)
access : write-only

Enumeration:

0 : Disable

On read, this bit should result it in 0

1 : Enable

When 1 is written mask bit gets cleared

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 5 - 36 (32 bit)
access : read-write


GPIO_GRP_INTR_STS

GPIO Interrupt 0 Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_GRP_INTR_STS GPIO_GRP_INTR_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_STATUS WAKEUP RESERVED1 MASK_SET MASK_CLEAR RESERVED2

INTERRUPT_STATUS : Interrupt status is available in this bit when interrupt is enabled and generated. When 1 is written, interrupt gets cleared.
bits : 0 - 0 (1 bit)
access : read-write

WAKEUP : Double ranked version of wakeup. Gets set when wakeup is enabled and occurs. When 1 is written it gets cleared
bits : 1 - 2 (2 bit)
access : read-only

RESERVED1 : Reserved1
bits : 2 - 4 (3 bit)
access : read-write

MASK_SET : Gives zero on read
bits : 3 - 6 (4 bit)
access : read-write

MASK_CLEAR : Gives zero on read
bits : 4 - 8 (5 bit)
access : read-write

RESERVED2 : Reserved2
bits : 5 - 36 (32 bit)
access : read-write


WORD_LOAD_REG

Word Load
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WORD_LOAD_REG WORD_LOAD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WORD_LOAD RESERVED1

WORD_LOAD : Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits.
bits : 0 - 15 (16 bit)
access : read-write

RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write


PORT_CLEAR_REG

Port Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_CLEAR_REG PORT_CLEAR_REG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_CLEAR RESERVED1

PORT_CLEAR : Clears the pin when corresponding bit is high. Writing zero has no effect.
bits : 0 - 15 (16 bit)
access : write-only

RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only


PORT_MASKED_LOAD_REG

Port Masked Load Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_MASKED_LOAD_REG PORT_MASKED_LOAD_REG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_MASKED_LOAD RESERVED1

PORT_MASKED_LOAD : Only loads into pins which are not masked. On read, pass only status unmasked pins
bits : 0 - 15 (16 bit)
access : write-only

RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only



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