\n
address_offset : 0x0 Bytes (0x0)
size : 0x1260 byte (0x0)
mem_usage : registers
protection :
GPIO Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRECTION : Direction of the GPIO pin
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Output
1 : Enable
Input
End of enumeration elements list.
PORTMASK : Port mask value
bits : 1 - 2 (2 bit)
access : read-write
MODE : GPIO Pin Mode Used for GPIO Pin Muxing
bits : 2 - 7 (6 bit)
access : read-write
Enumeration:
0 : Mode0
000: Mode 0
1 : Mode1
001:Mode 1
2 : Mode2
010:Mode 2
3 : Mode3
011:Mode 3
4 : Mode4
100:Mode 4
5 : Mode5
101: Mode 5
6 : Mode6
110:Mode 6
7 : Mode7
111:Mode 7
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 6 - 13 (8 bit)
access : read-write
GROUP_INTERRUPT1_ENABLE : When set, the corresponding GPIO is pin is selected for group intr 1 generation
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : Enable
enable the gpio group interrupt
0 : Disable
disable the gpio group interrupt1
End of enumeration elements list.
GROUP_INTERRUPT1_POLARITY : Decides the active value of the pin to be considered for group interrupt 1 generation
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
group interrupt gets generated when gpio input pin status is zero
1 : Enable
grp interrupt gets generated when gpio input pin status is 1
End of enumeration elements list.
GROUP_INTERRUPT2_ENABLE : When set, the corresponding GPIO is pin is selected for group intr 2 generation
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : Enable
enable the gpio group interrupt2
0 : Disable
disable the gpio group interrupt2
End of enumeration elements list.
GROUP_INTERRUPT2_POLARITY : Decides the active value of the pin to be considered for group interrupt 2 generation
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
group interrupt gets generated when gpio input pin status is zero
1 : Enable
grp interrupt gets generated when gpio input pin status is 1
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write
RESERVED3 : Reserved3
bits : 16 - 47 (32 bit)
access : read-write
Port Load
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_LOAD : Loads the value on to pin on write. And reads the value of load register on read
bits : 0 - 15 (16 bit)
access : read-write
RES : RES
bits : 16 - 47 (32 bit)
access : read-only
GPIO Interrupt Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEVEL_HIGH_ENABLE : enables interrupt generation when pin level is 1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
disabled
1 : Enable
Interrupt enabled
End of enumeration elements list.
LEVEL_LOW_ENABLE : enables interrupt generation when pin level is 0
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
disabled
1 : Enable
Interrupt enabled
End of enumeration elements list.
RISE_EDGE_ENABLE : enables interrupt generation when rising edge is detected on pin
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
disabled
1 : Enable
Interrupt enabled
End of enumeration elements list.
FALL_EDGE_ENABLE : enables interrupt generation when Falling edge is detected on pin
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
disabled
1 : Enable
Interrupt enabled
End of enumeration elements list.
MASK : Masks the interrupt. Interrupt will still be seen in status register when enabled
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Interrupt masked
1 : Enable
Interrupt unmasked
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 5 - 12 (8 bit)
access : read-write
PIN_NUMBER : GPIO Pin to be chosen for interrupt generation
bits : 8 - 19 (12 bit)
access : read-write
PORT_NUMBER : GPIO Port to be chosen for interrupt generation
bits : 12 - 25 (14 bit)
access : read-write
RESERVED2 : Reserved2
bits : 14 - 45 (32 bit)
access : read-write
GPIO Interrupt 0 Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AND_OR : AND/OR
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
AND
1 : Enable
OR
End of enumeration elements list.
LEVEL_EDGE : Level/Edge
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Level
1 : Enable
Edge
End of enumeration elements list.
ENABLE_WAKEUP : For wakeup generation, actual pin status has to be seen(before double ranking point)
bits : 2 - 4 (3 bit)
access : read-write
ENABLE_INTERRUPT : Enable Interrupt
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Enable
End of enumeration elements list.
MASK : Mask
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Mask
1 : Enable
unmask
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 5 - 36 (32 bit)
access : read-write
Port Toggle Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PORT_TOGGLE : Toggles the pin when corresponding bit is high. Writing zero has not effect.
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only
Port Read Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PORT_READ : Reads the value on GPIO pins irrespective of the pin mode.
bits : 0 - 15 (16 bit)
access : read-only
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-only
Bit Load
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIT_LOAD : Loads 0th bit on to the pin on write. And reads the value on pin on read into 0th bit
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : Reserved1
bits : 1 - 32 (32 bit)
access : read-write
Port Set Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PORT_SET : Sets the pin when corresponding bit is high. Writing zero has no effect.
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only
GPIO Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTERRUPT_STATUS : Gets set when interrupt is enabled and occurs.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 has not effect
1 : Enable
When 1 is written it gets cleared. Also clears rise edge and fall edge status bits
End of enumeration elements list.
RISE_EDGE_STATUS : Gets set when rise edge is enabled and occurs.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 has not effect
1 : Enable
When 1 is written it gets cleared.
End of enumeration elements list.
FALL_EDGE_STATUS : Gets set when Fall edge is enabled and occurs.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 has not effect
1 : Enable
When 1 is written it gets cleared.
End of enumeration elements list.
MASK_SET : Mask set
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : Disable
On read, this bit should result it in 0
1 : Enable
When 1 is written mask bit will get set
End of enumeration elements list.
MASK_CLEAR : Mask Clear
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : Disable
On read, this bit should result it in 0
1 : Enable
When 1 is written mask bit gets cleared
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 5 - 36 (32 bit)
access : read-write
GPIO Interrupt 0 Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTERRUPT_STATUS : Interrupt status is available in this bit when interrupt is enabled and generated. When 1 is written, interrupt gets cleared.
bits : 0 - 0 (1 bit)
access : read-write
WAKEUP : Double ranked version of wakeup. Gets set when wakeup is enabled and occurs. When 1 is written it gets cleared
bits : 1 - 2 (2 bit)
access : read-only
RESERVED1 : Reserved1
bits : 2 - 4 (3 bit)
access : read-write
MASK_SET : Gives zero on read
bits : 3 - 6 (4 bit)
access : read-write
MASK_CLEAR : Gives zero on read
bits : 4 - 8 (5 bit)
access : read-write
RESERVED2 : Reserved2
bits : 5 - 36 (32 bit)
access : read-write
Word Load
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WORD_LOAD : Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
Port Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PORT_CLEAR : Clears the pin when corresponding bit is high. Writing zero has no effect.
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only
Port Masked Load Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PORT_MASKED_LOAD : Only loads into pins which are not masked. On read, pass only status unmasked pins
bits : 0 - 15 (16 bit)
access : write-only
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : write-only
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