MCU_CAL_RO_TIMEPERIOD_READ

MCU_CAL_REF_CLK_SETTLE_REG

MCU_CAL_RC_TIMEPERIOD_READ

MCU_CAL_REF_CLK_TIEMPERIOD_REG

MCU_CAL_TIMER_CLOCK_PERIOD

MCU_CAL_TEMP_PROG_REG

MCU_CAL_START_REG

TIMEPERIOD_RO : Calibrated RO timeperiod
bits : 0 - 24 (25 bit)
access : read-only

RESERVED1 : reser
bits : 25 - 56 (32 bit)
access : read-only

XTAL_SETTLE : no of 32khz clocks for xtal 40mhz clk to settle
bits : 0 - 6 (7 bit)
access : read-write

RESERVED1 : reser
bits : 7 - 22 (16 bit)
access : read-only

VALID_RC_TIMEPERIOD : Valid signal for reading RC timeperiod calibrated
bits : 16 - 32 (17 bit)
access : read-only

VALID_RO_TIMEPERIOD : Valid signal for reading RO timeperiod
bits : 17 - 34 (18 bit)
access : read-only

RESERVED2 : reser
bits : 18 - 49 (32 bit)
access : read-only

TIMEPERIOD_RC : Calibrated RC timeperiod
bits : 0 - 24 (25 bit)
access : read-only

RESERVED1 : reser
bits : 25 - 56 (32 bit)
access : read-only

TIMEPERIOD_REF_CLK : timeperiod of reference clk with each bit corresponding to granularity of 2^27 = 1us
bits : 0 - 23 (24 bit)
access : read-write

RESERVED1 : reser
bits : 24 - 55 (32 bit)
access : read-only

RTC_TIMER_CLK_PERIOD : RTC timer clock period programmed by SOC
bits : 0 - 24 (25 bit)
access : read-write

RESERVED1 : reser
bits : 25 - 55 (31 bit)
access : read-only

SPI_RTC_TIMER_CLK_PERIOD_APPLIED : Indicated SOC programmed rtc_timer clock period is applied at KHz clock domain
bits : 31 - 62 (32 bit)
access : read-only

BYPASS_CALIB_PG : To bypass power gating and keep all the blocks always on
bits : 0 - 0 (1 bit)
access : read-write

RESERVED1 : reser
bits : 1 - 16 (16 bit)
access : read-only

MAX_TEMP_CHANGE : maximum temperature change after which rc calibration must be trigger
bits : 16 - 36 (21 bit)
access : read-write

TEMP_TRIGGER_TIME_SEL : temperature trigger time select
bits : 21 - 43 (23 bit)
access : read-write

PERIODIC_TEMP_CALIB_EN : Enable periodic checking of temperature
bits : 23 - 46 (24 bit)
access : read-write

RTC_TIMER_PERIOD_MUX_SEL : rtc timer period mux select
bits : 24 - 48 (25 bit)
access : read-write

RESERVED2 : reser
bits : 25 - 56 (32 bit)
access : read-only

ALPHA_RO : alpha = 1/2^alpha_ro , averaging factor of RO timeperiod T = alpha(t_inst) + (1- alpha )t_prev
bits : 0 - 2 (3 bit)
access : read-write

ALPHA_RC : alpha = 1/2^alpha_rc , averaging factor of RC timeperiod T = alpha(t_inst) + (1- alpha )t_prev
bits : 3 - 8 (6 bit)
access : read-write

NO_OF_RO_CLKS : 2^no_of_ro_clks no of clocks of ro clock counts for no of rc clocks in that time to measure timeperiod
bits : 6 - 15 (10 bit)
access : read-write

NO_OF_RC_CLKS : 2^no_of_rc_clocks = no of rc clocks used in calibration
bits : 10 - 22 (13 bit)
access : read-write

RC_SETTLE_TIME : no of clocks of RO for the RC clk to settle when enabled
bits : 13 - 28 (16 bit)
access : read-write

RO_TRIGGER_TIME_SEL : ro trigger time select
bits : 16 - 33 (18 bit)
access : read-write

RC_TRIGGER_TIME_SEL : rc trigger time select
bits : 18 - 38 (21 bit)
access : read-write

PERIODIC_RO_CALIB_EN : periodically calibrate RO timeperiod based ro trigger time sel
bits : 21 - 42 (22 bit)
access : read-write

PERIODIC_RC_CALIB_EN : periodically calibrate RC timeperiod based rc trigger time sel
bits : 22 - 44 (23 bit)
access : read-write

START_CALIB_RO : to initiate RO calibration
bits : 23 - 46 (24 bit)
access : write-only

START_CALIB_RC : to initiate RC calibration
bits : 24 - 48 (25 bit)
access : write-only

RC_XTAL_MUX_SEL : xtal mux select
bits : 25 - 50 (26 bit)
access : read-write

LOW_POWER_TRIGGER_SEL : power trigger select
bits : 26 - 52 (27 bit)
access : read-write

VBATT_TRIGGER_TIME_SEL : trigger to ipmu block for checking vbatt status periodicaly
bits : 27 - 56 (30 bit)
access : read-write

RESERVED1 : reser
bits : 30 - 61 (32 bit)
access : read-write