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WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

MCU_WWD_INTERRUPT_TIMER

MCU_WWD_MODE_AND_RSTART

MCU_WWD_KEY_ENABLE

MCU_WWD_SYSTEM_RESET_TIMER

MCU_WWD_WINDOW_TIMER

MCU_WWD_ARM_STUCK_EN


MCU_WWD_INTERRUPT_TIMER

WATCHDOG interrupt timer register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCU_WWD_INTERRUPT_TIMER MCU_WWD_INTERRUPT_TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWD_INTERRUPT_TIMER RESERVED1

WWD_INTERRUPT_TIMER : Watchdog Timer programming values
bits : 0 - 4 (5 bit)
access : read-write

RESERVED1 : reser
bits : 5 - 36 (32 bit)
access : read-only


MCU_WWD_MODE_AND_RSTART

WATCHDOG mode and restart register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCU_WWD_MODE_AND_RSTART MCU_WWD_MODE_AND_RSTART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWD_MODE_RSTART RESERVED1 WWD_MODE_EN_STATUS RESERVED2

WWD_MODE_RSTART : restart pulse to restart watchdog timer
bits : 0 - 0 (1 bit)
access : read-write

RESERVED1 : reser
bits : 1 - 16 (16 bit)
access : read-only

WWD_MODE_EN_STATUS : Watchdog timer mode
bits : 16 - 39 (24 bit)
access : read-write

RESERVED2 : reser
bits : 24 - 55 (32 bit)
access : read-only


MCU_WWD_KEY_ENABLE

watchdog key enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCU_WWD_KEY_ENABLE MCU_WWD_KEY_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWD_KEY_ENABLE

WWD_KEY_ENABLE : enable access to program Watch dog registers
bits : 0 - 31 (32 bit)
access : write-only


MCU_WWD_SYSTEM_RESET_TIMER

MCU watchdog system reset register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCU_WWD_SYSTEM_RESET_TIMER MCU_WWD_SYSTEM_RESET_TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWD_SYSTEM_RESET_TIMER RESERVED1

WWD_SYSTEM_RESET_TIMER : Watch dog soc reset delay timer programming values
bits : 0 - 4 (5 bit)
access : read-write

RESERVED1 : reser
bits : 5 - 36 (32 bit)
access : read-only


MCU_WWD_WINDOW_TIMER

watchdog window timer register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCU_WWD_WINDOW_TIMER MCU_WWD_WINDOW_TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINDOW_TIMER RESERVED1

WINDOW_TIMER : watchdog window timer
bits : 0 - 3 (4 bit)
access : read-write

RESERVED1 : reser
bits : 4 - 35 (32 bit)
access : read-only


MCU_WWD_ARM_STUCK_EN

watchdog arm stuck enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCU_WWD_ARM_STUCK_EN MCU_WWD_ARM_STUCK_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED1 PROCESSOR_STUCK_RESET_EN RESERVED2 PROCESSOR_STUCK_RESET_EN_ RESERVED3

RESERVED1 : reser
bits : 0 - 15 (16 bit)
access : read-only

PROCESSOR_STUCK_RESET_EN : Enable to reset M4 core on seeing LOCKUP signal
bits : 16 - 32 (17 bit)
access : write-only

RESERVED2 : reser
bits : 17 - 40 (24 bit)
access : read-write

PROCESSOR_STUCK_RESET_EN_ : Read signal for processor stuck reset enable
bits : 24 - 48 (25 bit)
access : read-only

RESERVED3 : reser
bits : 25 - 56 (32 bit)
access : read-write



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