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GPDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x71C byte (0x0)
mem_usage : registers
protection :

Registers

LINK_LIST_PTR_REGS

MISC_CHANNEL_CTRL_REG_CHNL

FIFO_CONFIG_REGS

PRIORITY_CHNL_REGS

SRC_ADDR_REG_CHNL

DEST_ADDR_REG_CHNL

CHANNEL_CTRL_REG_CHNL


Link List Register for channel 0 to 7
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LINK_LIST_PTR_REGS LINK_LIST_PTR_REGS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINK_LIST_PTR_REG_CHNL

LINK_LIST_PTR_REG_CHNL : This is the address of the memory location from which we get our next descriptor
bits : 0 - 31 (32 bit)
access : read-write


MISC_CHANNEL_CTRL_REG_CHNL

Misc Channel Control Register for channel 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CHANNEL_CTRL_REG_CHNL MISC_CHANNEL_CTRL_REG_CHNL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_BURST_SIZE DEST_DATA_BURST SRC_DATA_BURST DEST_CHNL_ID SRC_CHNL_ID DMA_PROT MEM_FILL_ENABLE MEM_ONE_FILL

AHB_BURST_SIZE : Burst size
bits : 0 - 2 (3 bit)
access : read-write

DEST_DATA_BURST : Burst writes in beats to destination.(000000-64 beats .....111111-63 beats)
bits : 3 - 11 (9 bit)
access : read-write

SRC_DATA_BURST : Burst writes in beats from source(000000-64 beats .....111111-63 beats)
bits : 9 - 23 (15 bit)
access : read-write

DEST_CHNL_ID : This is the destination channel Id to which the data is sent. Must be set up prior to DMA_CHANNEL_ENABLE
bits : 15 - 35 (21 bit)
access : read-write

SRC_CHNL_ID : This is the source channel Id, from which the data is fetched. must be set up prior to DMA_CHANNEL_ENABLE
bits : 21 - 47 (27 bit)
access : read-write

DMA_PROT : Protection level to go with the data. It will be concatenated with 1 b1 as there will be no opcode fetching and directly assign to hprot in AHB interface
bits : 27 - 56 (30 bit)
access : read-write

MEM_FILL_ENABLE : Enable for memory filling with either 1s or 0s.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled the memory filling

End of enumeration elements list.

MEM_ONE_FILL : Select for memory filling with either 1s or 0s.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : Disable

Memory fill with 0s.

1 : Enable

Memory fill with 1s.

End of enumeration elements list.


FIFO_CONFIG_REGS

FIFO Configuration Register for channel 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_CONFIG_REGS FIFO_CONFIG_REGS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_STRT_ADDR FIFO_SIZE RESERVED1

FIFO_STRT_ADDR : Starting row address of channel
bits : 0 - 5 (6 bit)
access : read-write

FIFO_SIZE : Channel size
bits : 6 - 17 (12 bit)
access : read-write

RESERVED1 : Reserved1
bits : 12 - 43 (32 bit)
access : read-only


PRIORITY_CHNL_REGS

Priority Register for channel 0 to 7
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRIORITY_CHNL_REGS PRIORITY_CHNL_REGS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY_CH RESERVED1

PRIORITY_CH : Set a value between 2 b00 to 2 b11. The channel having highest number is the highest priority channel.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : 00

priority level 0

1 : 01

priority level 1

2 : 10

priority level 2

3 : 11

priority level 3

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 2 - 33 (32 bit)
access : read-only


SRC_ADDR_REG_CHNL

Source Address Register for channel 0 to 7
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC_ADDR_REG_CHNL SRC_ADDR_REG_CHNL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_ADDR

SRC_ADDR : This is the address of the memory location from which we get our next descriptor
bits : 0 - 31 (32 bit)
access : read-write


DEST_ADDR_REG_CHNL

Source Address Register for channel 0 to 7
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEST_ADDR_REG_CHNL DEST_ADDR_REG_CHNL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEST_ADDR

DEST_ADDR : This is the destination address to whih the data is sent
bits : 0 - 31 (32 bit)
access : read-write


CHANNEL_CTRL_REG_CHNL

Channel Control Register for channel 0 to 7
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL_CTRL_REG_CHNL CHANNEL_CTRL_REG_CHNL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_BLK_SIZE TRNS_TYPE DMA_FLOW_CTRL MSTR_IF_FETCH_SEL MSTR_IF_SEND_SEL DEST_DATA_WIDTH SRC_DATA_WIDTH SRC_ALIGN LINK_LIST_ON LINK_LIST_MSTR_SEL SRC_ADDR_CONTIGUOUS DEST_ADDR_CONTIGUOUS RETRY_ON_ERROR LINK_INTERRUPT SRC_FIFO_MODE DEST_FIFO_MODE RESERVED1

DMA_BLK_SIZE : This is data to be transmitted. Loaded at the beginning of the DMA transfer and decremented at every dma transaction.
bits : 0 - 11 (12 bit)
access : read-write

TRNS_TYPE : DMA transfer type
bits : 12 - 25 (14 bit)
access : read-write

Enumeration:

0 : 00

Memory to Memory

1 : 01

memory to peripheral

2 : 10

peripheral to memory

3 : 11

peripheral to peripheral

End of enumeration elements list.

DMA_FLOW_CTRL : DMA flow control
bits : 14 - 29 (16 bit)
access : read-write

Enumeration:

0 : 00

RPDMAC :can be set for any type of transfers

1 : 01

source peripheral : typically set for peripheral to memory

2 : 10

peripheral to memory destination peripheral : typically set for memory to peripheral

3 : 11

src_and_dest peripheral : Typically set for peripheral to peripheral

End of enumeration elements list.

MSTR_IF_FETCH_SEL : This selects the MASTER IF from which data to be fetched
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : 0

0:MSTR-0 for fetch (from src)

1 : 1

1:MSTR-0 for fetch (from src)

End of enumeration elements list.

MSTR_IF_SEND_SEL : This selects the MASTER IF from which data to be sent
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

0 : 0

0:MSTR-0 for send (to destination)

1 : 1

1:MSTR-1 for send (to destination)

End of enumeration elements list.

DEST_DATA_WIDTH : Data transfer to destination.
bits : 18 - 37 (20 bit)
access : read-write

Enumeration:

0 : 00

08 bits of data on the bus

1 : 01

16 bits of data on the bus

2 : 10

32 bits of data on the bus

3 : 11

reserved1

End of enumeration elements list.

SRC_DATA_WIDTH : Data transfer from source.
bits : 20 - 41 (22 bit)
access : read-write

Enumeration:

0 : 00

08 bits of data on the bus

1 : 01

16 bits of data on the bus

2 : 10

32 bits of data on the bus

3 : 11

reserved2

End of enumeration elements list.

SRC_ALIGN : Reserved.Value set to 0 We do not do any singles. We just do burst, save first 3 bytes in to residue buffer in one cycle, In the next cycle send 4 bytes to fifo, save 3 bytes in to residue. This continues on.
bits : 22 - 44 (23 bit)
access : read-write

LINK_LIST_ON : This mode is set, when we do link listed operation
bits : 23 - 46 (24 bit)
access : read-write

LINK_LIST_MSTR_SEL : This mode is set, when we do link listed operation
bits : 24 - 48 (25 bit)
access : read-write

Enumeration:

0 : 0

0:M0 will be used to fetch desc

1 : 1

1:M1 will be used to fetch desc

End of enumeration elements list.

SRC_ADDR_CONTIGUOUS : Indicates Address is contiguous from previous
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : 0

0

1 : 1

1:Indicates Address is contiguous from previous

End of enumeration elements list.

DEST_ADDR_CONTIGUOUS : Indicates Address is contiguous from previous
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : 0

0

1 : 1

1:Indicates Address is contiguous from previous

End of enumeration elements list.

RETRY_ON_ERROR : When this bit is set, if we recieve HRESPERR, We will retry the DMA for that channel.
bits : 27 - 54 (28 bit)
access : read-write

LINK_INTERRUPT : This bit is set in link list descriptor.Hard ware will send an interrupt when the DMA transfer is done for the corresponding link list address
bits : 28 - 56 (29 bit)
access : read-write

SRC_FIFO_MODE : If set to 1 source address will not be incremented(means fifo mode for source)
bits : 29 - 58 (30 bit)
access : read-write

DEST_FIFO_MODE : If set to 1 destination address will not be incremented(means fifo mode for destination)
bits : 30 - 60 (31 bit)
access : read-write

RESERVED1 : Reserved1
bits : 31 - 62 (32 bit)
access : read-only



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