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GPDMA

Peripheral Memory Blocks

address_offset : 0x1084 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

INTERRUPT_REG

DMA_CHNL_SQUASH_REG

DMA_CHNL_LOCK_REG

INTERRUPT_MASK_REG

INTERRUPT_STAT_REG

DMA_CHNL_ENABLE_REG


INTERRUPT_REG

Interrupt Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERRUPT_REG INTERRUPT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDMAC_INT_STAT RESERVED1

GPDMAC_INT_STAT : Interrupt Status
bits : 0 - 7 (8 bit)
access : read-write

RESERVED1 : reserved1
bits : 8 - 39 (32 bit)
access : read-only


DMA_CHNL_SQUASH_REG

This register used for enable DMA channel squash
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_CHNL_SQUASH_REG DMA_CHNL_SQUASH_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH_DIS RESERVED1

CH_DIS : CPU Will be masked to write zeros, CPU is allowed write 1 only
bits : 0 - 7 (8 bit)
access : read-write

RESERVED1 : Reserved1
bits : 8 - 39 (32 bit)
access : read-only


DMA_CHNL_LOCK_REG

This register used for enable DMA channel squash
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_CHNL_LOCK_REG DMA_CHNL_LOCK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_LOCK RESERVED1

CHNL_LOCK : When set entire DMA block transfer is done, before other DMA request is serviced
bits : 0 - 7 (8 bit)
access : read-write

RESERVED1 : Reserved1
bits : 8 - 39 (32 bit)
access : read-only


INTERRUPT_MASK_REG

Interrupt Mask Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERRUPT_MASK_REG INTERRUPT_MASK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED1 LINK_LIST_FETCH_MASK TFR_DONE_MASK RESERVED2

RESERVED1 : reserved1
bits : 0 - 7 (8 bit)
access : read-write

LINK_LIST_FETCH_MASK : Linked list fetch done interrupt bit mask control. By default, descriptor fetch done interrupt is masked.
bits : 8 - 23 (16 bit)
access : read-write

TFR_DONE_MASK : Transfer done interrupt bit mask control.
bits : 16 - 39 (24 bit)
access : read-write

RESERVED2 : reserved2
bits : 24 - 55 (32 bit)
access : read-write


INTERRUPT_STAT_REG

Interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERRUPT_STAT_REG INTERRUPT_STAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRESP_ERR0 LINK_LIST_FETCH_DONE0 TFR_DONE0 GPDMAC_ERR0 HRESP_ERR1 LINK_LIST_FETCH_DONE1 TFR_DONE1 GPDMAC_ERR1 HRESP_ERR2 LINK_LIST_FETCH_DONE2 TFR_DONE2 GPDMAC_ERR2 HRESP_ERR3 LINK_LIST_FETCH_DONE3 TFR_DONE3 GPDMAC_ERR3 HRESP_ERR4 LINK_LIST_FETCH_DONE4 TFR_DONE4 GPDMAC_ERR4 HRESP_ERR5 LINK_LIST_FETCH_DONE5 TFR_DONE5 GPDMAC_ERR5 HRESP_ERR6 LINK_LIST_FETCH_DONE6 TFR_DONE6 GPDMAC_ERR6 HRESP_ERR7 LINK_LIST_FETCH_DONE7 TFR_DONE7 GPDMAC_ERR7

HRESP_ERR0 : DMA error bit
bits : 0 - 0 (1 bit)
access : read-write

LINK_LIST_FETCH_DONE0 : This bit indicates the status of linked list descriptor fetch done for channel 0
bits : 1 - 2 (2 bit)
access : read-write

TFR_DONE0 : This bit indicates the status of DMA transfer done interrupt for channel 0
bits : 2 - 4 (3 bit)
access : read-write

GPDMAC_ERR0 : transfer size or burst size or h size mismatch error
bits : 3 - 6 (4 bit)
access : read-write

HRESP_ERR1 : HRESP error bit
bits : 4 - 8 (5 bit)
access : read-write

LINK_LIST_FETCH_DONE1 : This bit indicates the status of linked list descriptor fetch done for channel 1
bits : 5 - 10 (6 bit)
access : read-write

TFR_DONE1 : This bit indicates the status of DMA transfer done interrupt for channel 1.
bits : 6 - 12 (7 bit)
access : read-write

GPDMAC_ERR1 : transfer size or burst size or h size mismatch error
bits : 7 - 14 (8 bit)
access : read-write

HRESP_ERR2 : HRESP error bit
bits : 8 - 16 (9 bit)
access : read-write

LINK_LIST_FETCH_DONE2 : This bit indicates the status of linked list descriptor fetch done for channel 2.
bits : 9 - 18 (10 bit)
access : read-write

TFR_DONE2 : This bit indicates the status of DMA transfer done interrupt for channel 2.
bits : 10 - 20 (11 bit)
access : read-write

GPDMAC_ERR2 : transfer size or burst size or h size mismatch error
bits : 11 - 22 (12 bit)
access : read-write

HRESP_ERR3 : HRESP error bit
bits : 12 - 24 (13 bit)
access : read-write

LINK_LIST_FETCH_DONE3 : This bit indicates the status of linked list descriptor fetch done for channel 3.
bits : 13 - 26 (14 bit)
access : read-write

TFR_DONE3 : This bit indicates the status of DMA transfer done interrupt for channel 3.
bits : 14 - 28 (15 bit)
access : read-write

GPDMAC_ERR3 : transfer size or burst size or h size mismatch error
bits : 15 - 30 (16 bit)
access : read-write

HRESP_ERR4 : HRESP error bit
bits : 16 - 32 (17 bit)
access : read-write

LINK_LIST_FETCH_DONE4 : This bit indicates the status of linked list descriptor fetch done for channel 4.
bits : 17 - 34 (18 bit)
access : read-write

TFR_DONE4 : This bit indicates the status of DMA transfer done interrupt for channel 4.
bits : 18 - 36 (19 bit)
access : read-write

GPDMAC_ERR4 : transfer size or burst size or h size mismatch error
bits : 19 - 38 (20 bit)
access : read-write

HRESP_ERR5 : HRESP error bit
bits : 20 - 40 (21 bit)
access : read-write

LINK_LIST_FETCH_DONE5 : This bit indicates the status of linked list descriptor fetch done for channel 5.
bits : 21 - 42 (22 bit)
access : read-write

TFR_DONE5 : This bit indicates the status of DMA transfer done interrupt for channel 5.
bits : 22 - 44 (23 bit)
access : read-write

GPDMAC_ERR5 : transfer size or burst size or h size mismatch error
bits : 23 - 46 (24 bit)
access : read-write

HRESP_ERR6 : HRESP error bit
bits : 24 - 48 (25 bit)
access : read-only

LINK_LIST_FETCH_DONE6 : This bit indicates the status of linked list descriptor fetch done for channel 6.
bits : 25 - 50 (26 bit)
access : read-write

TFR_DONE6 : This bit indicates the status of DMA transfer done interrupt for channel 6.
bits : 26 - 52 (27 bit)
access : read-write

GPDMAC_ERR6 : transfer size or burst size or h size mismatch error
bits : 27 - 54 (28 bit)
access : read-write

HRESP_ERR7 : HRESP error bit
bits : 28 - 56 (29 bit)
access : read-write

LINK_LIST_FETCH_DONE7 : This bit indicates the status of linked list descriptor fetch done for channel 7.
bits : 29 - 58 (30 bit)
access : read-write

TFR_DONE7 : This bit indicates the status of DMA transfer done interrupt for channel 7.
bits : 30 - 60 (31 bit)
access : read-write

GPDMAC_ERR7 : transfer size or burst size or h size mismatch error
bits : 31 - 62 (32 bit)
access : read-write


DMA_CHNL_ENABLE_REG

This register used for enable DMA channel
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_CHNL_ENABLE_REG DMA_CHNL_ENABLE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH_ENB RESERVED1

CH_ENB : CWhen a bit is set to one, it indicates, corresponding channel is enabled for dma operation
bits : 0 - 7 (8 bit)
access : read-write

RESERVED1 : Reserved1
bits : 8 - 39 (32 bit)
access : read-only



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