\n
address_offset : 0x0 Bytes (0x0)
size : 0x214 byte (0x0)
mem_usage : registers
protection :
Control register1 for DAC
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ENDAC_FIFO_CONFIG : This bit activates the DAC path in Aux ADC-DAC controller. Data samples will be played on DAC only when this bit is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : Enable
Enable fifo configuration of DAC
0 : Disable
Disable fifo configuration of DAC
End of enumeration elements list.
DAC_STATIC_MODE : This bit is used to select non-FIFO mode in DAC.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : Enable
Static mode is enabled. Data written to the DAC_DATA_REG will not be written to the FIFO. It will be played on DAC directly. Only single sample can be held at a time
0 : Disable
FIFO mode enabled. Data written to the DAC_DATA_REG is written to the FIFO in this mode. In either of these modes, data will be driven to the DAC only when dac_enable is set.
End of enumeration elements list.
DAC_FIFO_FLUSH : This bit is used to flush the DAC FIFO.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : Enable
Flush dac FIFO
0 : Disable
Do not flush
End of enumeration elements list.
DAC_FIFO_THRESHOLD : These bits control the DAC FIFO threshold. When used by DMA, this will act as almost full threshold. For TA, it acts as almost empty threshold
bits : 3 - 8 (6 bit)
access : read-write
DAC_ENABLE_F : This bit is used to enable AUX DAC controller ,valid only when DAC enable is happpen
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : Enable
Enable DAC Controller
0 : Disable
Disable DAC Controller
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0
bits : 7 - 15 (9 bit)
access : read-write
DAC_TO_CTRL_ADC : When set, AUX-DAC control is handed over to Aux ADC-DAC controller. By default, AUX-DAC is under the control of baseband.
bits : 9 - 18 (10 bit)
access : read-write
RESERVED2 : Reserved2
bits : 10 - 41 (32 bit)
access : read-write
This is configuration register0 to explain the bit map for ADC channels
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_BITMAP : This field explain the bit map for ADC channels
bits : 0 - 31 (32 bit)
access : read-write
Writing to this register will fill DAC FIFO for streaming Data to DAC
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
AUXDAC_DATA : Writing to this register will fill DAC FIFO for streaming Data to DAC
bits : 0 - 9 (10 bit)
access : write-only
RESERVED1 : Reserved1
bits : 10 - 41 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
AUXADC Data Read through Register.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
AUXADC_DATA : AUXADC Data Read through Register
bits : 0 - 11 (12 bit)
access : read-only
AUXADC_CH_ID : Channel ID of AUX DATA sample, Valid only in FIFO mode
bits : 12 - 27 (16 bit)
access : read-only
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_OFFSET : This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
ADC detection threshold control 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADC_INPUT_DETECTION_THRESHOLD_0 : The value against which the ADC output has to be compared is to be programmed in this register
bits : 0 - 7 (8 bit)
access : read-write
COMP_LESS_THAN_EN : When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls below the programmed Aux ADC detection threshold.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : Enable
Enable less than mode
0 : Disable
Disable less than mode
End of enumeration elements list.
COMP_GRTR_THAN_EN : When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is greater than the programmed Aux ADC detection threshold..
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : Enable
Enable grater than mode
0 : Disable
Disable grater than mode
End of enumeration elements list.
COMP_EQ_EN : When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is equal to the programmed Aux ADC detection threshold
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : Enable
Enable compare equal bit
0 : Disable
Disable compare equal bit
End of enumeration elements list.
RANGE_COMPARISON_ENABLE : When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls within the range specified in AUX ADC Detection threshold0 and AUX ADC Detection threshold1
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : Enable
Enable range comparison
0 : Disable
Disable range comparison
End of enumeration elements list.
ADC_INPUT_DETECTION_THRESHOLD_1 : Carries upper two bits of ADC detection threshold
bits : 12 - 25 (14 bit)
access : read-write
RESERVED1 : Reserved1
bits : 14 - 45 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CH_FREQ_VALUE : This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved1
bits : 16 - 47 (32 bit)
access : read-write
ADC detection threshold control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADC_INPUT_DETECTION_THRESHOLD_2 : The value against which the ADC output has to be compared is to be programmed in this register.
bits : 0 - 7 (8 bit)
access : read-write
COMP_LESS_THAN_EN : When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output falls below the programmed Aux ADC detection threshold.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : Enable
Enable less than mode
0 : Disable
Disable less than mode
End of enumeration elements list.
COMP_GRTR_THAN_EN : When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is greater than the programmed Aux ADC detection threshold.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : Enable
Enable grater than mode
0 : Disable
Disable grater than mode
End of enumeration elements list.
COMP_EQ_EN : When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is equal to the programmed Aux ADC detection threshold.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : Enable
Enable compare equal bit
0 : Disable
Disable compare equal bit
End of enumeration elements list.
ADC_DETECTION_THRESHOLD_2_UPPER_BITS : Upper 2 bits of ADC detection threshold 2
bits : 11 - 23 (13 bit)
access : read-write
RESERVED1 : Reserved1
bits : 13 - 44 (32 bit)
access : read-write
This register explain configuration parameter for AUXADC
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : Reserved1
bits : 0 - 16 (17 bit)
access : read-write
AUXADC_INP_SEL : Mux select for positive input of adc
bits : 17 - 38 (22 bit)
access : read-write
AUXADC_INN_SEL : Mux select for negetive input of adc
bits : 22 - 47 (26 bit)
access : read-write
AUXADC_DIFF_MODE : AUX ADC Differential Mode select
bits : 26 - 52 (27 bit)
access : read-write
RESERVED2 : Reserved2
bits : 27 - 58 (32 bit)
access : read-write
This register explain configuration parameter for AUXADC
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADC_SEQ_CTRL_PING_PONG : To enable/disable per channel DAM mode (One-hot coding)
bits : 0 - 15 (16 bit)
access : read-write
ADC_SEQ_CTRL_DMA_MODE : To enable/disable per channel ping-pong operation (One-hot coding).
bits : 16 - 47 (32 bit)
access : read-write
This register explain VDD BBP ID
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BPP_ID : Channel id for bbp samples.
bits : 0 - 3 (4 bit)
access : read-write
BPP_EN : Enables Aux-ADC samples to BBP
bits : 4 - 8 (5 bit)
access : read-write
AUX_ADC_BPP_EN : Enable Indication for BBP
bits : 5 - 10 (6 bit)
access : read-write
RESERVED1 : Reserved1
bits : 6 - 13 (8 bit)
access : read-write
VAD_ID : Enable VAD identification
bits : 8 - 19 (12 bit)
access : read-write
VAD_EN : Enable VAD
bits : 12 - 24 (13 bit)
access : read-write
RESERVED2 : RESERVED2
bits : 13 - 28 (16 bit)
access : read-write
DISCONNET_MODE : Per channel discontinuous mode enable signal. When discontinuous mode is enabled, data is sampled only once from that channel and the enable bit is reset to 0.
bits : 16 - 47 (32 bit)
access : read-write
This register explain start address of first/second buffer corresponding to the channel location ADC INT MEM 2
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PROG_WR_DATA : These 32-bits specifies the start address of first/second buffer corresponding to the channel location ADC INT MEM
bits : 0 - 31 (32 bit)
access : read-write
This register explain ADC INT MEM2.
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PROG_WR_DATA : These 10-bits specify the buffer length of first/second buffer corresponding to the channel location ADC INT MEM2
bits : 0 - 9 (10 bit)
access : read-write
PROG_WR_ADDR : These bits correspond to the address of the internal memory basing on the channel number, whose information we want to program
bits : 10 - 24 (15 bit)
access : read-write
PROG_WR_DATA1 : Valid bit for first/second buffers corresponding to ADC INT MEM2
bits : 15 - 30 (16 bit)
access : read-write
RESERVED3 : Reserved3
bits : 16 - 47 (32 bit)
access : read-write
This register is internal channel enable
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PER_CHANNEL_ENABLE : Enable bit for Each channel,like channel0 for bit0 to channel15 for bit15 etc
bits : 0 - 15 (16 bit)
access : read-write
RESERVED3 : Reserved3
bits : 16 - 46 (31 bit)
access : read-write
INTERNAL_DMA_ENABLE : When Set, Internal DMA will be used for reading ADC samples from ADC FIFO and writing them to ULP SRAM Memories.
bits : 31 - 62 (32 bit)
access : read-write
This register is enable PTAT for temperature sensor
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TS_PTAT_EN : BJT based Temperature sensor
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : Enable
Enable PTAT bit
0 : Disable
Disable PTAT bit
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 1 - 32 (32 bit)
access : read-write
ADC detection threshold control 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CLR_INTR : This bit is used to clear threshold detection interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : CLEAR_INTERRUPT
Clear the interrupt
0 : NO_EFFECT
Disable compare equal bit
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 1 - 8 (8 bit)
access : read-write
INTR_CLEAR_REG : If enabled, corresponding first_mem_switch_intr bits will be cleared.
bits : 8 - 31 (24 bit)
access : read-write
RESERVED2 : Reserved2
bits : 24 - 55 (32 bit)
access : read-write
Programs resistor bank, reference buffer and scaler
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : Reserved1
bits : 0 - 2 (3 bit)
access : read-write
REFBUF_EN : Reference buffer configuration 1 for enable 0 for disable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disable reference buffer enable bit
1 : Enable
Enable reference buffer enable bit
End of enumeration elements list.
REFBUF_VOLT_SEL : selection of voltage of reference buffer
bits : 4 - 11 (8 bit)
access : read-write
BOD_RES_EN : configuration of register bank 1 for enable and 0 for disable
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Disable register bank bit
1 : Enable
Enable register bank bit
End of enumeration elements list.
BOD_THRSH : Programmability for resistor bank
bits : 9 - 22 (14 bit)
access : read-write
RESERVED2 : Reserved2
bits : 14 - 45 (32 bit)
access : read-write
Programs comparators1 and comparators2
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CMP1_EN : To enable comparator1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable comparator1
1 : Enable
Enable comparator1
End of enumeration elements list.
CMP1_EN_FILTER : To enable filter for comparator 1
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable filter for comparator1
1 : Enable
Enable filter to comparator1
End of enumeration elements list.
CMP1_HYST : Programmability to control hysteresis of comparator1
bits : 2 - 5 (4 bit)
access : read-write
CMP1_MUX_SEL_P : Select for positive input of comparator_1
bits : 4 - 11 (8 bit)
access : read-write
Enumeration:
0 : comp1_p0
external pin as positive input for comparator1
1 : comp1_p1
external pin as positive input for comparator1
2 : DAC
DAC as positive input for comparator1
3 : reference_buffer_out
reference_buffer_out as positive input for comparator1
4 : reference_scaler_out
reference_scaler_out as positive input for comparator1
5 : register_bank_out
register_bank_out as positive input for comparator1
6 : opamp1
opamp1 as positive input for comparator1
7 : opamp2
opamp2 as positive input for comparator1
8 : opamp3
opamp3 as positive input for comparator1
End of enumeration elements list.
CMP1_MUX_SEL_N : Select for negative input of comparator_1
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : comp1_n0
external pin as negative input for comparator1
1 : comp1_n1
external pin as negative input for comparator1
2 : DAC
DAC as negative input for comparator1
3 : reference_buffer_out
reference_buffer_out as negative input for comparator1
4 : reference_scaler_out
reference_scaler_out as negative input for comparator1
5 : register_bank_out
register_bank_out as negative input for comparator1
6 : opamp1
opamp1 as negative input for comparator1
7 : opamp2
opamp2 as negative input for comparator1
8 : opamp3
opamp3 as negative input for comparator1
End of enumeration elements list.
CMP2_EN : To enable comparator 2
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
Disable comparator2
1 : Enable
Enable comparator2
End of enumeration elements list.
CMP2_EN_FILTER : To enable filter for comparator 2
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
Disable filter for comparator2
1 : Enable
Enable filter to comparator2
End of enumeration elements list.
CMP2_HYST : Programmability to control hysteresis of comparator2
bits : 14 - 29 (16 bit)
access : read-write
CMP2_MUX_SEL_P : Select for positive input of comparator_2
bits : 16 - 35 (20 bit)
access : read-write
Enumeration:
0 : comp2_p0
external pin as positive input for comparator2
1 : comp2_p1
external pin as positive input for comparator2
2 : DAC
DAC as positive input for comparator2
3 : reference_buffer_out
reference_buffer_out as positive input for comparator2
4 : reference_scaler_out
reference_scaler_out as positive input for comparator2
5 : register_bank_out
register_bank_out as positive input for comparator2
6 : opamp1
opamp1 as positive input for comparator2
7 : opamp2
opamp2 as positive input for comparator2
8 : opamp3
opamp3 as positive input for comparator2
End of enumeration elements list.
CMP2_MUX_SEL_N : Select for negative input of comparator_2
bits : 20 - 43 (24 bit)
access : read-write
Enumeration:
0 : comp2_n0
external pin as negative input for comparator2
1 : comp2_n1
external pin as negative input for comparator2
2 : DAC
DAC as negative input for comparator2
3 : reference_buffer_out
reference_buffer_out as negative input for comparator2
4 : reference_scaler_out
reference_scaler_out as negative input for comparator2
5 : register_bank_out
register_bank_out as negative input for comparator2
6 : opamp1
opamp1 as negative input for comparator2
7 : opamp2
opamp2 as negative input for comparator2
8 : opamp3
opamp3 as negative input for comparator2
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 24 - 55 (32 bit)
access : read-write
This register is AUX-ADC config2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : Reserved1
bits : 0 - 10 (11 bit)
access : read-write
AUXADC_CONFIG_ENABLE : Aux ADC Configuration Enable
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : Enable
ADC Configuration Enable
0 : Disable
Disable ADC Configuration
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 12 - 43 (32 bit)
access : read-write
This register is AUX-DAC config1
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
AUXDAC_EN_S : Enable signal DAC
bits : 0 - 0 (1 bit)
access : read-write
AUXDAC_OUT_MUX_EN : Aux OUT mux Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : Enable
DAC output is connected to PAD
0 : Disable
DAC output is not connected to PAD
End of enumeration elements list.
AUXDAC_OUT_MUX_SEL : AUXDAC OUT MUX SELECT Enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : Enable
DAC output is connected to PAD
0 : Disable
DAC output is not connected to PAD
End of enumeration elements list.
RESERVED1 : Reserved1
bits : 3 - 6 (4 bit)
access : read-write
AUXDAC_DATA_S : Satatic AUX Dac Data
bits : 4 - 17 (14 bit)
access : read-write
AUXDAC_DYN_EN : Satatic AUX Dac Data
bits : 14 - 28 (15 bit)
access : read-write
RESERVED2 : RESERVED2
bits : 15 - 46 (32 bit)
access : read-write
This register is AUX-LDO configuration
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LDO_CTRL : Enable ldo control field
bits : 0 - 3 (4 bit)
access : read-write
LDO_DEFAULT_MODE : ldo default mode enable
bits : 4 - 8 (5 bit)
access : read-write
BYPASS_LDO : bypass the LDO
bits : 5 - 10 (6 bit)
access : read-write
ENABLE_LDO : Turn LDO
bits : 6 - 12 (7 bit)
access : read-write
DYN_EN : Dynamic Enable
bits : 7 - 14 (8 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 8 - 39 (32 bit)
access : read-write
Mask interrupt register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
THRESHOLD_DETECTION_INTR_EN : When Cleared, threshold detection interrupt will be unmasked
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : MASK_INTERRUPT
When bit is set mask the interrupt
0 : UNMASK_EFFECT
When bit is clear unmask the interrupt
End of enumeration elements list.
DAC_FIFO_EMPTY_INTR_MASK : When Cleared, dac_FIFO_empty interrupt will be unmasked
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : MASK_INTERRUPT
When bit is set mask the interrupt
0 : UNMASK_EFFECT
When bit is clear unmask the interrupt
End of enumeration elements list.
DAC_FIFO_AEMPTY_INTR_MASK : When Cleared, adc FIFO full interrupt will be unmasked
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : MASK_INTERRUPT
When bit is set mask the interrupt
0 : UNMASK_EFFECT
When bit is clear unmask the interrupt
End of enumeration elements list.
ADC_FIFO_FULL_INTR_MASK : When Cleared, adc FIFO full interrupt will be unmasked
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : MASK_INTERRUPT
When bit is set mask the interrupt
0 : UNMASK_EFFECT
When bit is clear unmask the interrupt
End of enumeration elements list.
ADC_FIFO_AFULL_INTR_MASK : When Cleared, adc FIFO afull interrupt will be unmasked
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : MASK_INTERRUPT
When bit is set mask the interrupt
0 : UNMASK_EFFECT
When bit is clear unmask the interrupt
End of enumeration elements list.
ADC_FIFO_OVERFLOW_INTR_MASK : When Cleared, dac FIFO underrun interrupt will be unmasked
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : MASK_INTERRUPT
When bit is set mask the interrupt
0 : UNMASK_EFFECT
When bit is clear unmask the interrupt
End of enumeration elements list.
DAC_FIFO_UNDERRUN_INTR_MASK : When Cleared, dac FIFO underrun interrupt will be unmasked
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : MASK_INTERRUPT
When bit is set mask the interrupt
0 : UNMASK_EFFECT
When bit is clear unmask the interrupt
End of enumeration elements list.
FIRST_MEM_SWITCH_INTR_MASK : When Cleared, first_mem_switch_intr will be unmasked
bits : 7 - 29 (23 bit)
access : read-write
RESERVED1 : Reserved1
bits : 23 - 54 (32 bit)
access : read-write
Status interrupt register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ADC_THRESHOLD_DETECTION_INTR : This bit is set when ADC threshold matches with the programmed conditions This will be be cleared as soon as this interrupt is acknowledged by processor
bits : 0 - 0 (1 bit)
access : read-only
DAC_FIFO_EMPTY : Set when DAC FIFO is empty. This bit gets cleared when the DAC FIFO at least a single sample is available in DAC FIFO
bits : 1 - 2 (2 bit)
access : read-only
DAC_FIFO_AEMPTY : Set when the FIFO occupancy grater than or equal to DAC FIFO threshold.
bits : 2 - 4 (3 bit)
access : read-only
ADC_FIFO_FULL : Set when ADC FIFO is full,This bit gets cleared when data is read from the FIFO
bits : 3 - 6 (4 bit)
access : read-only
ADC_FIFO_AFULL : Set when ADC FIFO occupancy less than or equal to ADC FIFO threshold
bits : 4 - 8 (5 bit)
access : read-only
ADC_FIFO_OVERFLOW : Set when a write attempt is made to ADC FIFO when the FIFO is already full
bits : 5 - 10 (6 bit)
access : read-only
DAC_FIFO_UNDERRUN : Set when a read is done on DAC FIFO when the FIFO is empty
bits : 6 - 12 (7 bit)
access : read-only
FIRST_MEM_SWITCH_INTR : Interrupt indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation
bits : 7 - 29 (23 bit)
access : read-only
RESERVED1 : Reserved1
bits : 23 - 54 (32 bit)
access : read-only
Interrupt masked status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ADC_THRESHOLD_DETECTION_INTR_MASKED : Masked Interrupt. This bit is set when ADC threshold matches with the programmed conditions
bits : 0 - 0 (1 bit)
access : read-only
DAC_FIFO_EMPTY_MASKED : Masked Interrupt.Set when DAC FIFO is empty
bits : 1 - 2 (2 bit)
access : read-only
DAC_FIFO_AEMPTY_MASKED : Masked Interrupt. Set when the FIFO occupancy less than equal to DAC FIFO threshold.
bits : 2 - 4 (3 bit)
access : read-only
ADC_FIFO_FULL_MASKED : Masked Interrupt. Set when ADC FIFO is full.
bits : 3 - 6 (4 bit)
access : read-only
ADC_FIFO_AFULL_MASKED : Masked Interrupt. Set when ADC FIFO occupancy greater than ADC FIFO threshold
bits : 4 - 8 (5 bit)
access : read-only
ADC_FIFO_OVERFLOW_MASKED : Masked Interrupt. Set when a write attempt is made to ADC FIFO when the FIFO is already full.
bits : 5 - 10 (6 bit)
access : read-only
DAC_FIFO_UNDERRUN_MASKED : Masked Interrupt. Set when a read is done on DAC FIFO when the FIFO is empty.
bits : 6 - 12 (7 bit)
access : read-only
FIRST_MEM_SWITCH_INTR_MASKED : Masked Interrupt status indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation
bits : 7 - 29 (23 bit)
access : read-only
RESERVED1 : Reserved1
bits : 23 - 54 (32 bit)
access : read-only
Interrupt masked status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DAC_FIFO_FULL : Set when DAC FIFO is full. In word mode, FIFO will be shown as full unless there is space for 16-bits.
bits : 0 - 0 (1 bit)
access : read-only
DAC_FIFO_AFULL : Set when DAC FIFO occupancy greater than FIFO threshold
bits : 1 - 2 (2 bit)
access : read-only
ADC_FIFO_EMPTY : Set when FIFO is empty. This bit gets cleared when the ADC FIFO is not empty.
bits : 2 - 4 (3 bit)
access : read-only
ADC_FIFO_AEMPTY : Set when the FIFO occupancy less than ADC FIFO threshold
bits : 3 - 6 (4 bit)
access : read-only
DAC_FIFO_EMPTY : Set when FIFO is empty. This bit gets cleared when the DAC FIFO is not empty.
bits : 4 - 8 (5 bit)
access : read-only
DAC_FIFO_AEMPTY : Set when the FIFO occupancy less than DAC FIFO threshold
bits : 5 - 10 (6 bit)
access : read-only
ADC_FIFO_FULL : Set when ADC FIFO is full. This bit gets cleared when data is read from the FIFO.
bits : 6 - 12 (7 bit)
access : read-only
ADC_FIFO_AFULL : Set when ADC FIFO occupancy greater than ADC FIFO threshold.
bits : 7 - 14 (8 bit)
access : read-only
RESERVED1 : Reserved1
bits : 8 - 39 (32 bit)
access : read-only
Control register1 for ADC
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADC_ENABLE : This bits activates the ADC path in Aux ADC-DAC controller.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : Enable
Enable ADC
0 : Disable
Disable ADC
End of enumeration elements list.
ADC_STATIC_MODE : This bit is used to select non-FIFO mode in ADC.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : Enable
Static mode enable here data directly to register not in FIFO
0 : Disable
FIFO mode enabled here data directly to FIFO.
End of enumeration elements list.
ADC_FIFO_FLUSH : This bit is used to flush the ADC FIFO
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : Enable
Flush ADC FIFO
0 : Disable
Do not flush
End of enumeration elements list.
ADC_FIFO_THRESHOLD : These bits control the ADC FIFO threshold. When used by DMA, this will act as almost empty threshold. For TA, it acts as almost full threshold.
bits : 3 - 8 (6 bit)
access : read-write
ADC_MULTIPLE_CHAN_ACTIVE : This bit is used to control the auxadc sel signal going to the Aux ADC.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : Enable
Data will be sampled from four ADC channels in sequential order and written to the receive FIFO in the same order.
0 : Disable
Data will be sampled from the programmed ADC channel
End of enumeration elements list.
ADC_CH_SEL_MSB : It is recommended to write these bits to 0
bits : 7 - 15 (9 bit)
access : read-write
BYPASS_NOISE_AVG : ADC in Bypass noise avg mode.
bits : 9 - 18 (10 bit)
access : read-write
EN_ADC_CLK : Enable AUX ADC Divider output clock
bits : 10 - 20 (11 bit)
access : read-write
RESERVED1 : Reserved1
bits : 11 - 22 (12 bit)
access : read-write
ADC_CH_SEL_LS : Aux ADC channel number from which the data has to be sampled This is valid only when adc multiple channel active is zero. When channel number is greater than three, upper bits should also be programmed ADC CHANNEL SELECT MS to bits in this register
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : CHANNEL_0
channel 0
1 : CHANNEL_1
channel 1
2 : CHANNEL_2
channel 2
3 : CHANNEL_3
channel 3
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 14 - 40 (27 bit)
access : read-write
ADC_NUM_PHASE : ADC number of phase
bits : 27 - 54 (28 bit)
access : read-write
RESERVED3 : Reserved3
bits : 28 - 59 (32 bit)
access : read-write
This is configuration register1 to explain the bit map for ADC channels
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_BITMAP : This field explain the bit map for ADC channels
bits : 0 - 31 (32 bit)
access : read-write
DAC clock division register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DAC_CLK_DIV_FAC : These bits control the DAC clock division factor
bits : 0 - 9 (10 bit)
access : read-write
RESERVED1 : Reserved1
bits : 10 - 41 (32 bit)
access : read-write
This is configuration register2 to explain the bit map for ADC channels
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_BITMAP : This field explain the bit map for ADC channels
bits : 0 - 31 (32 bit)
access : read-write
ADC clock division register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADC_CLK_DIV_FAC : These bits control the Total-Duration of the ADC clock
bits : 0 - 9 (10 bit)
access : read-write
RESERVED1 : Reserved1
bits : 10 - 25 (16 bit)
access : read-write
ADC_CLK_ON_DUR : These bits control the On-Duration of the ADC clock
bits : 16 - 40 (25 bit)
access : read-write
RESERVED2 : Reserved2
bits : 25 - 56 (32 bit)
access : read-write
This is configuration register3 to explain the bit map for ADC channels
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_BITMAP : This field explain the bit map for ADC channels
bits : 0 - 31 (32 bit)
access : read-write
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