Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection :
Clock Enable Set Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_UART1_APB_CLK_EN : Writing 1 to this enables clock to UART1 APB Interface.Writing 0 to this has no effect.
bits : 0 - 0 (1 bit)
access : read-write
MCUHP_UART1_CLK_EN : Writing 1 to this enables clock to UART1 Controller.Writing 0 to this has no effect.
bits : 1 - 2 (2 bit)
access : read-write
MCUHP_UART2_APB_CLK_EN : Writing 1 to this enables clock to UART2 APB Interface.Writing 0 to this has no effect.
bits : 2 - 4 (3 bit)
access : read-write
MCUHP_UART2_CLK_EN : Writing 1 to this enables clock to UART2 Controller.Writing 0 to this has no effect.
bits : 3 - 6 (4 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 4 - 12 (9 bit)
access : read-write
MCUHP_CT_CLK_EN : Writing 1 to this enables clock to Configurable Timers.Writing 0 to this has no effect.
bits : 9 - 18 (10 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 10 - 22 (13 bit)
access : read-write
MCUHP_DMA_CLK_EN : Writing 1 to this disables clock to DMA.Writing 0 to this has no effect.
bits : 13 - 26 (14 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 14 - 31 (18 bit)
access : read-write
MCUHP_CRC_CLK_EN : Writing 1 to this enables clock to CRC Accelerator.Writing 0 to this has no effect.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED4 : It is recommended to write these bits to 0.
bits : 19 - 39 (21 bit)
access : read-write
MCUHP_ETH_AHB_CLK_EN : Writing 1 to this enables clock to Ethernet Controller AHB Interface.Writing 0 to this has no effect.
bits : 21 - 42 (22 bit)
access : read-write
MCUHP_RNG_CLK_EN : Writing 1 to this enables clock to Random-Number-Generator
bits : 22 - 44 (23 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 23 - 47 (25 bit)
access : read-write
MCUHP_CCI_AHB_CLK_EN : Writing 1 to this enables clock to CCI AHB Interface.Writing 0 to this has no effect.
bits : 25 - 50 (26 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 27 - 55 (29 bit)
access : read-write
MCUHP_SDMEM_CLK_EN : Writing 1 to this enables clock to SD-MEM Controller.Writing 0 to this has no effect.
bits : 29 - 58 (30 bit)
access : read-write
RESERVED7 : It is recommended to write these bits to 0.
bits : 30 - 60 (31 bit)
access : read-write
MCUHP_ULP_CLK_EN : Writing 1 to this enables clock to MCU-ULPDomain.Writing 0 to this has no effect.
bits : 31 - 62 (32 bit)
access : read-write
Clock Enable Set Register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 4 (5 bit)
access : read-write
MCUHP_EFUSE_CLK_EN : Writing 1 to this enables clock to eFUSE Controller.Writing 0 to this has no effect.
bits : 5 - 10 (6 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 6 - 18 (13 bit)
access : read-write
MCUHP_QSPI_CLK_EN : Writing 1 to this enables clock to SPI Flash Controller.Writing 0 to this has no effect.
bits : 13 - 26 (14 bit)
access : read-write
MCUHP_QSPI_CLK_SYNC_EN : Writing 1 to this enables SPI Flash Controller clock in synchronous with Processor Clock.Writing 0 to this has no effect.
bits : 14 - 28 (15 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 15 - 30 (16 bit)
access : read-write
MCUHP_EGPIO_CLK_EN : Writing 1 to this enables clock to Enhanced-GPIO Controller.Writing 0 to this has no effect.
bits : 16 - 32 (17 bit)
access : read-write
MCUHP_I2C_CLK_EN : Writing 1 to this enables clock to I2C-1 Controller.Writing 0 to this has no effect.
bits : 17 - 34 (18 bit)
access : read-write
MCUHP_I2C2_CLK_EN : Writing 1 to this enables clock to I2C-2 Controller.Writing 0 to this has no effect.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED4 : It is recommended to write these bits to 0.
bits : 19 - 38 (20 bit)
access : read-write
MCUHP_SIO_CLK_EN : Writing 1 to this enables clock to SIO Controller.Writing 0 to this has no effect.
bits : 20 - 40 (21 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 21 - 46 (26 bit)
access : read-write
MCUHP_PERI_CLK_EN : Writing 1 to this enables clock source to Peripherals.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_ICACHE_CLK_EN : Writing 1 to this enables clock to Generic-SPI Master.Writing 0 to this has no effect.
bits : 27 - 54 (28 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 28 - 59 (32 bit)
access : read-write
Clock Enable Clear Register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 4 (5 bit)
access : read-write
MCUHP_EFUSE_CLK_EN : Writing 1 to this disables clock to eFUSE Controller.Writing 0 to this has no effect.
bits : 5 - 10 (6 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 6 - 18 (13 bit)
access : read-write
MCUHP_QSPI_CLK_EN : Writing 1 to this disables clock to SPI Flash Controller.Writing 0 to this has no effect.
bits : 13 - 26 (14 bit)
access : read-write
MCUHP_QSPI_CLK_SYNC_EN : Writing 1 to this disables SPI Flash Controller clock in synchronous with Processor Clock. Writing 0 to this has no effect.
bits : 14 - 28 (15 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 15 - 30 (16 bit)
access : read-write
MCUHP_EGPIO_CLK_EN : Writing 1 to this disables clock to Enhanced-GPIO Controller.Writing 0 to this has no effect.
bits : 16 - 32 (17 bit)
access : read-write
MCUHP_I2C_CLK_EN : Writing 1 to this disables clock to I2C-1 Controller.Writing 0 to this has no effect.
bits : 17 - 34 (18 bit)
access : read-write
MCUHP_I2C2_CLK_EN : Writing 1 to this disables clock to I2C-2 Controller.Writing 0 to this has no effect.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED4 : It is recommended to write these bits to 0.
bits : 19 - 38 (20 bit)
access : read-write
MCUHP_SIO_CLK_EN : Writing 1 to this disables clock to SIO Controller.Writing 0 to this has no effect.
bits : 20 - 40 (21 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 21 - 46 (26 bit)
access : read-write
MCUHP_PERI_CLK_EN : Writing 1 to this disables clock source to Peripherals.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_ICACHE_CLK_EN : Writing 1 to this disables clock to Generic-SPI Master.Writing 0 to this has no effect.
bits : 27 - 54 (28 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 28 - 59 (32 bit)
access : read-write
Clock Configuration Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_QSPI_CLK_SEL : Specifies the clock source for SPI Flash controller when independent clock source.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : 000
MCU-HP Reference Clock
1 : 001
Interface-PLL Clock
2 : 010
RESERVED1
3 : 011
SoC-PLL Clock
4 : 100
Output Clock is gated
5 : 101
Output Clock is gated
6 : 110
Output Clock is gated
7 : 111
Output Clock is gated
End of enumeration elements list.
MCUHP_QSPI_CLK_DIV_FAC : Specifies the clock division factor for SPI Flash Controller.
bits : 3 - 11 (9 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 9 - 19 (11 bit)
access : read-write
MCUHP_SSI_CLK_DIV_FAC : Specifies the clock division factor for for SPI/SSI Master.
bits : 11 - 25 (15 bit)
access : read-write
MCUHP_SSI_CLK_SEL : Specifies the clock source for SPI/SSI Master.
bits : 15 - 32 (18 bit)
access : read-write
Enumeration:
0 : 000
MCU-HP Reference Clock
1 : 001
SoC-PLL Clock
2 : 010
RESERVED1
3 : 011
Interface-PLL Clock
4 : 100
RESERVED2
5 : 101
RESERVED3
6 : 110
Output Clock is gated
7 : 111
Output Clock is gated
End of enumeration elements list.
MCUHP_ETH_CLK_SEL : Specifies the clock source for Ethernet RMII Controller.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : 0
Interface-PLL Clock
1 : 1
SoC-PLL Clock
End of enumeration elements list.
MCUHP_ETH_CLK_DIV_FAC : Specifies the clock division factor for Ethernet RMII Controller.
bits : 19 - 41 (23 bit)
access : read-write
MCUHP_ETH_CLK_DIV_SEL : Selects the Divider type for Ethernet Controller.
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : 0
EVEN Clock Divider output is selected
1 : 1
Clock Divider output is selected
End of enumeration elements list.
MCUHP_GSPI_CLK_SEL : Specifies the clock source for GSPI Controller.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : 000
RESERVED1
1 : 001
MCU-HP Reference Clock
2 : 010
SoC-PLL Clock
3 : 011
RESERVED2
4 : 100
Interface-PLL Clock
5 : 101
Output Clock is gated
6 : 110
Output Clock is gated
7 : 111
Output Clock is gated
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 27 - 58 (32 bit)
access : read-write
Clock Configuration Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_UART1_CLK_SEL : Specifies the clock source to be used for UART1 Controller.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : 000
MCU-HP Reference Clock
1 : 001
SoC-PLL Clock
2 : 010
RESERVED1
3 : 011
RESERVED2
4 : 100
Interface-PLL Clock
5 : 101
Output Clock is gated
6 : 110
Output Clock is gated
7 : 111
Output Clock is gated
End of enumeration elements list.
MCUHP_UART1_CLK_DIV_FAC : Specifies the clock division factor for UART1 Controller.
bits : 3 - 9 (7 bit)
access : read-write
MCUHP_UART2_CLK_SEL : Specifies the clock source to be used for UART2 Controller.
bits : 7 - 16 (10 bit)
access : read-write
Enumeration:
0 : 000
MCU-HP Reference Clock
1 : 001
SoC-PLL Clock
2 : 010
RESERVED1
3 : 011
Interface-PLL Clock
4 : 100
RESERVED2
5 : 101
Output Clock is gated
6 : 110
Output Clock is gated
7 : 111
Output Clock is gated
End of enumeration elements list.
MCUHP_UART2_CLK_DIV_FAC : Specifies the clock division factor for UART2 Controller.
bits : 10 - 23 (14 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 14 - 37 (24 bit)
access : read-write
MCUHP_CCI_CLK_DIV_FAC : Specifies the clock division factor for CCI Controller.
bits : 24 - 51 (28 bit)
access : read-write
MCUHP_QSPI_CLK_ODD_SEL : Selects the Divider type for SPI Flash Controller when independent clock source w.r.t Processor is selected.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : 0
EVEN Clock Divider output is selected
1 : 1
ODD Clock Divider output is selected
End of enumeration elements list.
MCUHP_UART1_FRAC_CLK_SEL : Selects the Divider type for UART1 Controller. 0 - Clock Swallow output is selected 1 - Fractional Clock Divider output is selected
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
0 : 0
Clock Swallow output is selected
1 : 1
Fractional Clock Divider output is selected
End of enumeration elements list.
MCUHP_UART2_FRAC_CLK_SEL : Selects the Divider type for UART2 Controller. 0 - Clock Swallow output is selected 1 - Fractional Clock Divider output is selected
bits : 30 - 60 (31 bit)
access : read-write
Enumeration:
0 : 0
Clock Swallow output is selected
1 : 1
Fractional Clock Divider output is selected
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 31 - 62 (32 bit)
access : read-write
Clock Configuration Register 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_CAN_CLK_DIV_FAC : Specifies the clock division factor for CAN Controller.
bits : 0 - 7 (8 bit)
access : read-write
MCUHP_EXT_CLK_SEL : Specifies the clock source to be used for External Clock.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : 0000
Output Clock is Gated
1 : 0001
High Freq RC Clock source
2 : 0010
XTAL Clock source.
3 : 0011
RESERVED1
4 : 0100
High Freq RO Clock source
5 : 0101
Doubler Clock
6 : 0110
RESERVED2
7 : 0111
Low Freq RC Clock source
8 : 1000
Low Freq XTAL Clock source
9 : 1001
Low Freq RO Clock source
10 : 1010
Interface-PLL Clock
11 : 1011
RESERVED3
12 : 1100
RESERVED4
13 : 1101
SoC-PLL Clock
14 : 1110
I2S-PLL Clock
15 : 1111
RESERVED5
End of enumeration elements list.
MCUHP_EXT_CLK_DIV_FAC : Specifies the clock division factor for External Clock.
bits : 12 - 29 (18 bit)
access : read-write
MCUHP_EXT_CLK_EN : Writing 1 to this enables the External clock on GPIO PAD.Writing 0 to this disables the External clock on GPIO PAD.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 19 - 50 (32 bit)
access : read-write
Clock Configuration Register 4
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to retain the contents by using read/modify write to this register.
bits : 0 - 20 (21 bit)
access : read-write
MCUHP_LP_CLK_SEL : Specifies the clock source to be used for Low-Power Clock.
bits : 21 - 43 (23 bit)
access : read-write
Enumeration:
0 : 000
Low Freq RC Clock source
1 : 001
Low Freq XTAL Clock source
2 : 010
Output Clock is gated
3 : 011
Low Freq RO Clock source
End of enumeration elements list.
RESERVED2 : It is recommended to retain the contents by using read/modify write to this register.
bits : 23 - 47 (25 bit)
access : read-write
MCUHP_ULP_DIV_FAC : Specifies the clock division factor for MCU ULP Domain source.
bits : 25 - 55 (31 bit)
access : read-write
MCUHP_CCI_CLK_SEL : Specifies the clock source to be used for Low-Power Clock.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : 0
RESERVED1
1 : 1
Interface-PLL Clock
End of enumeration elements list.
Clock Configuration Register 5
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_PROC_CLK_SEL : Specifies the clock source to be used for Processor.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : 0000
MCU-HP Reference Clock
1 : 0001
RESERVED1
2 : 0010
SoC-PLL Clock
3 : 0011
RESERVED2
4 : 0100
Interface-PLL Clock
5 : 0101
Low-Power Clock
6 : 0110
RESERVED3
7 : 0111
RESERVED4
End of enumeration elements list.
MCUHP_PROC_CLK_DIV_FAC : Specifies the clock division factor for Processor Clock.
bits : 4 - 13 (10 bit)
access : read-write
MCUHP_I2S_CLK_SEL : Specifies the clock source to be used for I2S Controller in Master Mode.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : 0
I2S-PLL Clock
1 : 1
RESERVED1
End of enumeration elements list.
MCUHP_I2S_CLK_DIV_FAC : Specifies the clock division factor for I2S Controller in Master Mode.
bits : 11 - 27 (17 bit)
access : read-write
MCUHP_CT_CLK_SEL : Specifies the clock source to be used for Configurable Timers.
bits : 17 - 36 (20 bit)
access : read-write
Enumeration:
0 : 000
MCU-HP Reference Clock
1 : 001
Interface-PLL Clock
2 : 010
SoC-PLL Clock
3 : 011
RESERVED1
4 : 100
Output Clock is gated
5 : 101
Output Clock is gated
6 : 110
Output Clock is gated
7 : 111
Output Clock is gated
End of enumeration elements list.
MCUHP_CT_CLK_DIV_FAC : Specifies the clock division factor for Configurable Timers.
bits : 20 - 45 (26 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 26 - 53 (28 bit)
access : read-write
MCUHP_ULP_CLK_SEL : Specifies the divider type to be selected to MCU ULP Domain source.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : 0
Clock Divider output is selected
1 : 1
Odd Clock Divider output is selected
End of enumeration elements list.
RESERVED2 : It is recommended to retain the contents by using read/modify write to this register.
bits : 29 - 60 (32 bit)
access : read-write
Clock Enable Clear Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_UART1_APB_CLK_EN : Writing 1 to this disables clock to UART1 APB Interface.Writing 0 to this has no effect.
bits : 0 - 0 (1 bit)
access : read-write
MCUHP_UART1_CLK_EN : Writing 1 to this disables clock to UART1 Controller.Writing 0 to this has no effect.
bits : 1 - 2 (2 bit)
access : read-write
MCUHP_UART2_APB_CLK_EN : Writing 1 to this disables clock to UART2 APB Interface.Writing 0 to this has no effect.
bits : 2 - 4 (3 bit)
access : read-write
MCUHP_UART2_CLK_EN : Writing 1 to this disables clock to UART2 Controller.Writing 0 to this has no effect.
bits : 3 - 6 (4 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 4 - 12 (9 bit)
access : read-write
MCUHP_CT_CLK_EN : Writing 1 to this disables clock to Configurable Timers.Writing 0 to this has no effect.
bits : 9 - 18 (10 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 10 - 22 (13 bit)
access : read-write
MCUHP_DMA_CLK_EN : Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
bits : 13 - 26 (14 bit)
access : read-write
MCUHP_DMA_CLK_EN : Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
bits : 13 - 26 (14 bit)
access : read-write
MCUHP_DMA_CLK_EN : Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
bits : 13 - 26 (14 bit)
access : read-write
MCUHP_DMA_CLK_EN : Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
bits : 13 - 26 (14 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 14 - 31 (18 bit)
access : read-write
MCUHP_CRC_CLK_EN : Writing 1 to this disables clock to CRC Accelerator.Writing 0 to this has no effect.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED4 : It is recommended to write these bits to 0.
bits : 19 - 39 (21 bit)
access : read-write
MCUHP_ETH_AHB_CLK_EN : Writing 1 to this disables clock to Ethernet Controller AHB Interface.Writing 0 to this has no effect.
bits : 21 - 42 (22 bit)
access : read-write
MCUHP_RNG_CLK_EN : Writing 1 to this disables clock to Random-Number-Generator.Writing 0 to this has no effect.
bits : 22 - 44 (23 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 23 - 47 (25 bit)
access : read-write
MCUHP_CCI_AHB_CLK_EN : Writing 1 to this disables clock to CCI AHB Interface.Writing 0 to this has no effect.
bits : 25 - 50 (26 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
MCUHP_CCI_CLK_EN : Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
bits : 26 - 52 (27 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 27 - 55 (29 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 27 - 55 (29 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 27 - 55 (29 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 27 - 55 (29 bit)
access : read-write
MCUHP_SDMEM_CLK_EN : Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
bits : 29 - 58 (30 bit)
access : read-write
MCUHP_SDMEM_CLK_EN : Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
bits : 29 - 58 (30 bit)
access : read-write
MCUHP_SDMEM_CLK_EN : Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
bits : 29 - 58 (30 bit)
access : read-write
MCUHP_SDMEM_CLK_EN : Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
bits : 29 - 58 (30 bit)
access : read-write
RESERVED7 : It is recommended to write these bits to 0.
bits : 30 - 60 (31 bit)
access : read-write
RESERVED7 : It is recommended to write these bits to 0.
bits : 30 - 60 (31 bit)
access : read-write
RESERVED7 : It is recommended to write these bits to 0.
bits : 30 - 60 (31 bit)
access : read-write
RESERVED7 : It is recommended to write these bits to 0.
bits : 30 - 60 (31 bit)
access : read-write
MCUHP_ULP_CLK_EN : Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
bits : 31 - 62 (32 bit)
access : read-write
MCUHP_ULP_CLK_EN : Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
bits : 31 - 62 (32 bit)
access : read-write
MCUHP_ULP_CLK_EN : Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
bits : 31 - 62 (32 bit)
access : read-write
MCUHP_ULP_CLK_EN : Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
bits : 31 - 62 (32 bit)
access : read-write
SDMEM Clock Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_SDMEM_CLK_DIV_FAC : Specifies the clock division factor for SDMEM Controller.
bits : 0 - 5 (6 bit)
access : read-write
MCUHP_SDMEM_CLK_SEL : Specifies the clock source to be used for SD-MEM(eMMC).
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : 000
SoC-PLL Clock
2 : 010
Interface-PLL Clock
3 : 011
RESERVED1
4 : 100
Output clock is disabled
5 : 101
Output clock is disabled
6 : 110
Output clock is disabled
7 : 111
Output clock is disabled
End of enumeration elements list.
MCUHP_SDMEM_CLK_DIV_SEL : Specifies the divider type to be selected to SDMEM Controller
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : 0
EVEN Clock Divider output is selected
1 : 1
Clock Divider output is selected
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 10 - 41 (32 bit)
access : read-write
Clock Status Register for Dynamic Clock Muxes
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 7 (8 bit)
access : read-write
MCUHP_PROC_CLK_SWITCHED : Status of Dynamic Clock Mux in Processor Clock Generation
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_QSPI_CLK_SWITCHED : Status of Dynamic Clock Mux in SPI Flash Controller Clock Generation
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_UART1_CLK_SWITCHED : Status of Dynamic Clock Mux in UART1 Clock Generation
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_UART2_CLK_SWITCHED : Status of Dynamic Clock Mux in UART2 Clock Generation
bits : 11 - 22 (12 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_GSPI_CLK_SWITCHED : Status of Dynamic Clock Mux in Generic SPI Master Clock Generation
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_SSI_CLK_SWITCHED : Status of Dynamic Clock Mux in SPI/SSI Master Clock Generation
bits : 13 - 26 (14 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_SDMEM_CLK_SWITCHED : Status of Dynamic Clock Mux in SD-MEM(eMMC) Clock Generation
bits : 14 - 28 (15 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_CT_CLK_SWITCHED : Status of Dynamic Clock Mux in Configurable Timer Clock Generation
bits : 15 - 30 (16 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 16 - 32 (17 bit)
access : read-write
MCUHP_I2S_CLK_SWITCHED : Status of Dynamic Clock Mux in I2S Clock Generation
bits : 17 - 34 (18 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_ETH_CLK_SWITCHED : Status of Dynamic Clock Mux in Ethernet RMII Clock Generation
bits : 18 - 36 (19 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 19 - 39 (21 bit)
access : read-write
MCUHP_LP_CLK_SWITCHED : Status of Dynamic Clock Mux in Low-Power Clock Generation
bits : 21 - 42 (22 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_EXT_CLK_SWITCHED : Status of Dynamic Clock Mux in External Clock Generation
bits : 22 - 44 (23 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUHP_CCI_CLK_SWITCHED : Status of Dynamic Clock Mux in CCI Clock Generation
bits : 23 - 46 (24 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
RESERVED4 : It is recommended to write these bits to 0.
bits : 24 - 54 (31 bit)
access : read-only
MCUHP_REF_CLK_SWITCHED : Status of Dynamic Clock Mux in Reference Clock Generation
bits : 31 - 62 (32 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
Clock Enable Set Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_GSPI_APB_CLK_EN : Writing 1 to this enables clock to Generic-SPI Master APB Interface.Writing 0 to this has no effect.
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0
bits : 1 - 3 (3 bit)
access : read-write
MCUHP_CAN_CLK_EN : Writing 1 to this enables clock to CAN Controller.Writing 0 to this has no effect.
bits : 3 - 6 (4 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 4 - 9 (6 bit)
access : read-write
MCUHP_UDMA_CLK_EN : Writing 1 to this enables clock to Micro-DMA.Writing 0 to this has no effect.
bits : 6 - 12 (7 bit)
access : read-write
MCUHP_I2C_APB_CLK_EN : Writing 1 to this enables clock to I2C-1 APB Interface.Writing 0 to this has no effect.
bits : 7 - 14 (8 bit)
access : read-write
MCUHP_I2C2_APB_CLK_EN : Writing 1 to this enables clock to I2C-2 APB Interface.Writing 0 to this has no effect.
bits : 8 - 16 (9 bit)
access : read-write
MCUHP_SSI_SLV_APB_CLK_EN : Writing 1 to this enables clock to SSI Slave APB Interface.Writing 0 to this has no effect.
bits : 9 - 18 (10 bit)
access : read-write
MCUHP_SSI_SLV_CLK_EN : Writing 1 to this enables clock to SSI Slave Controller.Writing 0 to this has no effect.
bits : 10 - 20 (11 bit)
access : read-write
MCUHP_QSPI_CLK_DIV_EN : Writing 1 to this enables clock to Clock dividers for SPI Flash Controller.Writing 0 to this has no effect.
bits : 11 - 22 (12 bit)
access : read-write
MCUHP_QSPI_AHB_CLK_EN : Writing 1 to this enables clock to AHB Interface for SPI Flash Controller.Writing 0 to this has no effect..
bits : 12 - 24 (13 bit)
access : read-write
MCUHP_I2S_CLK_EN : Writing 1 to this enables clock to I2S Controller in Master Mode.Writing 0 to this has no effect.
bits : 13 - 26 (14 bit)
access : read-write
MCUHP_I2S_INTF_CLK_EN : Writing 1 to this enables clock to I2S Interface.Writing 0 to this has no effect.
bits : 14 - 28 (15 bit)
access : read-write
MCUHP_I2S_APB_CLK_EN : Writing 1 to this enables clock to I2S APB Interface.Writing 0 to this has no effect.
bits : 15 - 30 (16 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 16 - 32 (17 bit)
access : read-write
MCUHP_QE_CLK_EN : Writing 1 to this enables clock to Quadrature Encoder.Writing 0 to this has no effect.
bits : 17 - 34 (18 bit)
access : read-write
MCUHP_MCPWM_CLK_EN : Writing 1 to this enables clock to Motor-Control PWM.Writing 0 to this has no effect.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED4 : It is recommended to write these bits to 0.
bits : 19 - 41 (23 bit)
access : read-write
MCUHP_SSI_APB_CLK_EN : Writing 1 to this enables clock to SPI/SSI Master APN Interface.Writing 0 to this has no effect.
bits : 23 - 46 (24 bit)
access : read-write
MCUHP_SSI_CLK_EN : Writing 1 to this enables clock to SPI/SSI Master Controller.Writing 0 to this has no effect.
bits : 24 - 48 (25 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 25 - 52 (28 bit)
access : read-write
MCUHP_ETH_CLK_EN : Writing 1 to this enables clock to Ethernet Controller.Writing 0 to this has no effect.
bits : 28 - 56 (29 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 29 - 60 (32 bit)
access : read-write
Clock Enable Clear Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUHP_GSPI_APB_CLK_EN : Writing 1 to this disables clock to Generic-SPI Master APB Interface.Writing 0 to this has no effect.
bits : 0 - 0 (1 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 1 - 3 (3 bit)
access : read-write
MCUHP_CAN_CLK_EN : Writing 1 to this disables clock to CAN Controller.Writing 0 to this has no effect.
bits : 3 - 6 (4 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 4 - 9 (6 bit)
access : read-write
MCUHP_UDMA_CLK_EN : Writing 1 to this disables clock to Micro-DMA.Writing 0 to this has no effect.
bits : 6 - 12 (7 bit)
access : read-write
MCUHP_I2C_APB_CLK_EN : Writing 1 to this disables clock to I2C-1 APB Interface.Writing 0 to this has no effect.
bits : 7 - 14 (8 bit)
access : read-write
MCUHP_I2C2_APB_CLK_EN : Writing 1 to this disables clock to I2C-2 APB Interface.Writing 0 to this has no effect.
bits : 8 - 16 (9 bit)
access : read-write
MCUHP_SSI_SLV_APB_CLK_EN : Writing 1 to this disables clock to SSI Slave APB Interface.Writing 0 to this has no effect.
bits : 9 - 18 (10 bit)
access : read-write
MCUHP_SSI_SLV_CLK_EN : Writing 1 to this disables clock to SSI Slave Controller.Writing 0 to this has no effect.
bits : 10 - 20 (11 bit)
access : read-write
MCUHP_QSPI_CLK_DIV_EN : Writing 1 to this disables clock to Clock dividers for SPI Flash Controller.Writing 0 to this has no effect.
bits : 11 - 22 (12 bit)
access : read-write
MCUHP_QSPI_AHB_CLK_EN : Writing 1 to this disables clock to AHB Interface for SPI Flash Controller.Writing 0 to this has no effect.
bits : 12 - 24 (13 bit)
access : read-write
MCUHP_I2S_CLK_EN : Writing 1 to this disables clock to I2S Controller in Master Mode.Writing 0 to this has no effect.
bits : 13 - 26 (14 bit)
access : read-write
MCUHP_I2S_INTF_CLK_EN : Writing 1 to this disables clock to I2S Interface.Writing 0 to this has no effect.
bits : 14 - 28 (15 bit)
access : read-write
MCUHP_I2S_APB_CLK_EN : Writing 1 to this disables clock to I2S APB Interface.Writing 0 to this has no effect.
bits : 15 - 30 (16 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 16 - 32 (17 bit)
access : read-write
MCUHP_QE_CLK_EN : Writing 1 to this disables clock to Quadrature Encoder.Writing 0 to this has no effect.
bits : 17 - 34 (18 bit)
access : read-write
MCUHP_MCPWM_CLK_EN : Writing 1 to this disables clock to Motor-Control PWM.Writing 0 to this has no effect.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED4 : It is recommended to write these bits to 0.
bits : 19 - 41 (23 bit)
access : read-write
MCUHP_SSI_APB_CLK_EN : Writing 1 to this disables clock to SPI/SSI Master APB Interface.Writing 0 to this has no effect.
bits : 23 - 46 (24 bit)
access : read-write
MCUHP_SSI_CLK_EN : Writing 1 to this disables clock to SPI/SSI Master Controller.Writing 0 to this has no effect.
bits : 24 - 48 (25 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 25 - 52 (28 bit)
access : read-write
MCUHP_ETH_CLK_EN : Writing 1 to this disables clock to Ethernet Controller.Writing 0 to this has no effect.
bits : 28 - 56 (29 bit)
access : read-write
RESERVED6 : It is recommended to write these bits to 0.
bits : 29 - 60 (32 bit)
access : read-write
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