Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xA8 byte (0x0)
mem_usage : registers
protection :
MCU-ULP Clock Enable Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to retain the contents by using read/modify write to this register.
bits : 0 - 3 (4 bit)
access : read-write
MCUULP_IR_CLK_EN : ULP IR receiver clock enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to IR Receiver.
1 : Enable
Writing 1 to this enables clock to IR Receiver.
End of enumeration elements list.
MCUULP_I2C_APB_CLK_EN : ULP I2C APB clock enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to I2C APB Interface.
1 : Enable
Writing 1 to this enables clock to I2C APB Interface.
End of enumeration elements list.
MCUULP_I2S_CLK_EN : ULP I2S clock enable
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to I2S Controller.
1 : Enable
Writing 1 to this enables clock to I2S Controller.
End of enumeration elements list.
MCUULP_SSI_APB_CLK_EN : ULP SSI APB clock enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to SPI/SSI Master APB Interface.
1 : Enable
Writing 1 to this enables clock to SPI/SSI Master APB Interface.
End of enumeration elements list.
MCUULP_SSI_CLK_EN : ULP SSI clock enable
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to SPI/SSI Master.
1 : Enable
Writing 1 to this enables clock to SPI/SSI Master.
End of enumeration elements list.
MCUULP_UART_APB_CLK_EN : ULP UART APB clock enable
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to UART APB Interface.
1 : Enable
Writing 1 to this enables clock to UART APB Interface.
End of enumeration elements list.
MCUULP_UART_CLK_EN : ULP UART clock enable
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to UART Controller.
1 : Enable
Writing 1 to this enables clock to UART Controller.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 11 - 24 (14 bit)
access : read-write
MCUULP_EGPIO_CLK_EN : ULP EGPIO clock enable
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to Enhanced-GPIO.
1 : Enable
Writing 1 to this enables clock to Enhanced-GPIO.
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 15 - 30 (16 bit)
access : read-write
MCUULP_FIM_CLK_EN : ULP FIM clock enable
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to FIM Engine.
1 : Enable
Writing 1 to this enables clock to FIM Engine.
End of enumeration elements list.
MCUULP_VAD_CLK_EN : ULP VAD clock enable
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to VAD Controller.
1 : Enable
Writing 1 to this enables clock to VAD Controller.
End of enumeration elements list.
RESERVED4 : It is recommended to retain the contents by using read/modify write to this register.
bits : 18 - 48 (31 bit)
access : read-write
MCUULP_TOUCH_APB_CLK_EN : ULP VAD clock enable
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to Touch Sensor APB Interface.
1 : Enable
Writing 1 to this enables clock to Touch Sensor APB Interface.
End of enumeration elements list.
MCU-ULP AHB Clock Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to retain the contents by using read/modify write to this register.
bits : 0 - 0 (1 bit)
access : read-write
MCUULP_PROC_CLK_SEL : ULP Processor clock select
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : 0000
MCU-ULP Reference Clock
1 : 0001
ro_32khz_clk
2 : 0010
rc_32khz_clk
3 : 0011
xtal_32khz_clk
4 : 0100
rc_32mhz_clk
5 : 0101
ro_hf_clk
6 : 0110
MCU-HP ULP Clock
7 : 0111
doubler_clk
8 : 1000
Output clock is gated
9 : 1001
Output clock is gated
10 : 1010
Output clock is gated
11 : 1011
Output clock is gated
12 : 1100
Output clock is gated
13 : 1101
Output clock is gated
14 : 1110
Output clock is gated
15 : 1111
Output clock is gated
End of enumeration elements list.
MCUULP_PROC_CLK_DIV_DAC : Specifies the clock division factor for AHB Interface Clock.
bits : 5 - 17 (13 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 13 - 44 (32 bit)
access : read-write
MCU-ULP SSI Master and I2C Clock Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUULP_I2C_CLK_EN : ULP I2C clock enables
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to I2C Controller.
1 : Enable
Writing 1 to this enables clock to I2C Controller.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 1 - 16 (16 bit)
access : read-write
MCUULP_SSI_CLK_DIV_EN : ULP SSI clock division enables
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to SPI/SSI Master Clock Dividers.
1 : Enable
Writing 1 to this enables clock to SPI/SSI Master Clock Dividers.
End of enumeration elements list.
MCUULP_SSI_CLK_DIV_FAC : Specifies the clock division factor for SPI/SSI Master Clock.
bits : 17 - 40 (24 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 24 - 51 (28 bit)
access : read-write
MCUULP_SSI_CLK_SEL : ULP SSI clock select
bits : 28 - 59 (32 bit)
access : read-write
Enumeration:
0 : 0000
MCU-ULP Reference Clock
1 : 0001
ro_32khz_clk
2 : 0010
rc_32khz_clk
3 : 0011
xtal_32khz_clk
4 : 0100
rc_32mhz_clk
5 : 0101
ro_hf_clk
6 : 0110
MCU-HP ULP Clock
7 : 0111
RESERVED1
8 : 1000
RESERVED2
9 : 1001
RESERVED3
10 : 1010
RESERVED4
11 : 1011
RESERVED5
12 : 1100
RESERVED6
13 : 1101
RESERVED7
14 : 1110
RESERVED8
15 : 1111
Output clock is gated
End of enumeration elements list.
MCU-ULP I2S Clock Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUULP_I2S_CLK_DIV_EN : ULP I2S clock division enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to I2S Clock Dividers.
1 : Enable
Writing 1 to this enables clock to I2S Clock Dividers.
End of enumeration elements list.
MCUULP_I2S_CLK_SEL : Specifies the clock source to be used for I2S Master
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : 0000
MCU-ULP Reference Clock
1 : 0001
ro_32khz_clk
2 : 0010
rc_32khz_clk
3 : 0011
xtal_32khz_clk
4 : 0100
rc_32mhz_clk
5 : 0101
ro_hf_clk
6 : 0110
MCU-HP ULP Clock
7 : 0111
doubler_clk
8 : 1000
i2s_pll_clk
9 : 1001
RESERVED1
10 : 1010
RESERVED2
11 : 1011
RESERVED3
12 : 1100
RESERVED4
13 : 1101
RESERVED5
14 : 1110
RESERVED6
15 : 1111
Output clock is gated
End of enumeration elements list.
MCUULP_I2S_CLK_DIV_FAC : Specifies the clock division factor for I2S Master Clock.
bits : 5 - 17 (13 bit)
access : read-write
MCUULP_I2S_MASTER_SLAVE_MODE : Enable I2S master or slave mode
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Slave
Writing 0 to this configures I2S to Slave Mode.
1 : Master
Writing 1 to this configures I2S to Master Mode.
End of enumeration elements list.
RESERVED1 : It is recommended to retain the contents by using read/modify write to this register.
bits : 14 - 31 (18 bit)
access : read-write
MCUULP_I2S_APB_CLK_EN : I2S APB clock enable
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables clock to I2S APB Interface.
1 : Enable
Writing 1 to this enables clock to I2S APB Interface.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 19 - 50 (32 bit)
access : read-write
MCU-ULP UART Clock Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUULP_UART_FRAC_CLK_SEL : Selects the Divider type for UART Controller.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Clock Swallow output is selected.
1 : 1
Fractional Clock Divider output is selected.
End of enumeration elements list.
MCUULP_UART_CLK_SEL : Specifies the clock source to be used for UART.
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : 0000
MCU-ULP Reference Clock.
1 : 0001
ro_32khz_clk.
2 : 0010
rc_32khz_clk.
3 : 0011
xtal_32khz_clk.
4 : 0100
rc_32mhz_clk.
5 : 0101
ro_hf_clk.
6 : 0110
MCU-HP ULP Clock.
7 : 0111
doubler_clk
8 : 1000
RESERVED1
9 : 1001
RESERVED2
10 : 1010
RESERVED3
11 : 1011
RESERVED4
12 : 1100
RESERVED5
13 : 1101
RESERVED6
14 : 1110
RESERVED7
15 : 1111
Output clock is gated
End of enumeration elements list.
MCUULP_UART_CLK_DIV_FAC : Specifies the clock division factor for UART.
bits : 5 - 17 (13 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 13 - 44 (32 bit)
access : read-write
MCU-ULP Clock Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
MCUHP_UART_CLK_SWITCHED : Status of Dynamic Clock Mux in UART Clock Generation.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUULP_I2S_CLK_SWITCHED : Status of Dynamic Clock Mux in I2S Controller Clock Generation.
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 2 - 4 (3 bit)
access : read-only
MCUULP_PROC_CLK_SWITCHED : Status of Dynamic Clock Mux in AHB Interface Clock Generation.
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 4 - 8 (5 bit)
access : read-only
MCUULP_SSI_CLK_SWITCHED : Status of Dynamic Clock Mux in SPI/SSI Master Clock Generation.
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUULP_VAD_CLK_SWITCHED : Status of Dynamic Clock Mux in VAD Clock Generation.
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUULP_ADCDAC_CLK_SWITCHED : Status of Dynamic Clock Mux in Aux-ADC/DAC Clock Generation
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUULP_TIMER_CLK_SWITCHED : Status of Dynamic Clock Mux in Timer Clock Generation.
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUULP_TOUCH_CLK_SWITCHED : Status of Dynamic Clock Mux in Touch Sensor Clock Generation.
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUULP_VAD_FCLK_SWITCHED : Status of Dynamic Clock Mux in VAD Fast Clock Generation.
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
MCUULP_VAD_SCLK_SWITCHED : Status of Dynamic Clock Mux in VAD Slow Clock Generation
bits : 11 - 22 (12 bit)
access : read-only
Enumeration:
0 : 0
Clock switching is in progress
1 : 1
Clock got switched and output clock can be used
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 12 - 43 (32 bit)
access : read-only
MCU-ULP Touch Sensor Clock Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 0 (1 bit)
access : read-write
MCUULP_TOUCH_CLK_SEL : Specifies the clock source to be used for Touch Sensor.
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : 0000
MCU-ULP Reference Clock.
1 : 0001
ro_32khz_clk.
2 : 0010
rc_32khz_clk.
3 : 0011
xtal_32khz_clk.
4 : 0100
rc_32mhz_clk.
5 : 0101
ro_hf_clk.
6 : 0110
MCU-HP ULP Clock.
7 : 0111
RESERVED1
8 : 1000
RESERVED2
9 : 1001
RESERVED3
10 : 1010
RESERVED4
11 : 1011
RESERVED5
12 : 1100
RESERVED6
13 : 1101
RESERVED7
14 : 1110
RESERVED8
15 : 1111
Output clock is gated
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 5 - 17 (13 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 13 - 44 (32 bit)
access : read-write
MCU-ULP Timer Clock Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 0 (1 bit)
access : read-write
MCUULP_TIMER_CLK_SEL : Specifies the clock source to be used for Timer.
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : 0000
MCU-ULP Reference Clock.
1 : 0001
ro_32khz_clk.
2 : 0010
rc_32khz_clk.
3 : 0011
xtal_32khz_clk.
4 : 0100
rc_32mhz_clk.
5 : 0101
ro_hf_clk.
6 : 0110
MCU-HP ULP Clock.
7 : 0111
RESERVED1
8 : 1000
RESERVED2
9 : 1001
RESERVED3
10 : 1010
RESERVED4
11 : 1011
RESERVED5
12 : 1100
RESERVED6
13 : 1101
RESERVED7
14 : 1110
RESERVED8
15 : 1111
Output clock is gated
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 5 - 18 (14 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 14 - 45 (32 bit)
access : read-write
MCU-ULP Aux-ADC/DAC Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 0 (1 bit)
access : read-write
MCUULP_ADCDAC_CLK_SEL : Specifies the clock source to be used for Aux-ADC/DAC Controller
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : 0000
MCU-ULP Reference Clock.
1 : 0001
ro_32khz_clk.
2 : 0010
rc_32khz_clk.
3 : 0011
xtal_32khz_clk.
4 : 0100
rc_32mhz_clk.
5 : 0101
ro_hf_clk.
6 : 0110
MCU-HP ULP Clock.
7 : 0111
doubler_clk
8 : 1000
i2s_pll_clk
9 : 1001
RESERVED1
10 : 1010
RESERVED2
11 : 1011
RESERVED3
12 : 1100
RESERVED4
13 : 1101
RESERVED5
14 : 1110
RESERVED6
15 : 1111
Output clock is gated
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 5 - 17 (13 bit)
access : read-write
RESERVED3 : It is recommended to write these bits to 0.
bits : 13 - 44 (32 bit)
access : read-write
MCU-ULP VAD Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 0 (1 bit)
access : read-write
MCUULP_VAD_SCLK_SEL : Specifies the clock source to be used for VAD Slow Clock
bits : 1 - 4 (4 bit)
access : read-write
Enumeration:
0 : 000
ro_32khz_clk.
1 : 001
rc_32khz_clk.
2 : 010
xtal_32khz_clk.
3 : 011
RESERVED1.
4 : 100
RESERVED2.
5 : 101
RESERVED3.
6 : 110
RESERVED4.
7 : 111
Output clock is gated
End of enumeration elements list.
MCUULP_VAD_CLK_SEL : Specifies the clock source to be used for VAD Controller
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : 0
VAD Slow Clock
1 : 1
VAD Fast Clock
End of enumeration elements list.
MCUULP_VAD_FCLK_SEL : Specifies the clock source to be used for VAD Fast Clock
bits : 5 - 13 (9 bit)
access : read-write
Enumeration:
0 : 0000
MCU ULP AHB Interface clock.
1 : 0001
MCU-ULP Reference clock.
2 : 0010
rc_32mhz_clk.
3 : 0011
ro_hf_clk.
4 : 0100
MCU-HP ULP clock.
5 : 0101
RESERVED1
6 : 0110
RESERVED2
7 : 0111
RESERVED3
8 : 1000
RESERVED4
9 : 1001
RESERVED5
10 : 1010
RESERVED6
11 : 1011
RESERVED7
12 : 1100
RESERVED8
13 : 1101
RESERVED9
14 : 1110
RESERVED10
15 : 1111
Output clock is gated
End of enumeration elements list.
MCUULP_VAD_FCLK_DIV_FAC : Specifies the clock division factor for VAD Fast clock.
bits : 9 - 25 (17 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 17 - 48 (32 bit)
access : read-write
MCU-ULP Clock Enable Register 2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 11 (12 bit)
access : read-write
MCUULP_ADCDAC_CLK_EN : ULP ADC and DAC clock enable
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : 0
Writing 0 to this disables clock to Aux-ADC/DAC Controller.
1 : 1
Writing 1 to this enables clock to Aux-ADC/DAC Controller.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 13 - 29 (17 bit)
access : read-write
MCUULP_UDMA_CLK_EN : ULP UDMA clock enable
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : 0
Writing 0 to this disables clock to Aux-ADC/DAC Controller.
1 : 1
Writing 1 to this enables clock to Aux-ADC/DAC Controller.
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 18 - 49 (32 bit)
access : read-write
UULP APB Clock Configuration Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MCUULP_APB_CLK_DIV_FAC : Specifies the clock division factor for UULP APB Interface.
bits : 0 - 7 (8 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 1.
bits : 8 - 16 (9 bit)
access : read-write
RESERVED2 : It is recommended to write these bits to 0.
bits : 9 - 40 (32 bit)
access : read-write
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