Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x8 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection :
ULP_PERIPHERAL_POWER_CONTROL_SET
ULP_PERIPHERAL_POWER_CONTROL_CLEAR
ULP_SRAM_POWER_CONTROL_REG1_SET
ULP_SRAM_POWER_CONTROL_REG1_CLEAR
ULP_SRAM_POWER_CONTROL_REG4_SET
ULP_SRAM_POWER_CONTROL_REG4_CLEAR
ULP_SRAM_POWER_CONTROL_REG2_SET
ULP_SRAM_POWER_CONTROL_REG2_CLEAR
Enables power for HP-SRAM1, HP-SRAM2 and LP-SRAM domains.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL1_HPSRAM1_1 : It is enables power control1 to all banks in HP-SRAM1-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-1.
End of enumeration elements list.
PWRCTRL1_HPSRAM1_2 : It is enables power control1 to all banks in HP-SRAM1-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-2.
End of enumeration elements list.
PWRCTRL1_HPSRAM1_3 : It is enables power control1 to all banks in HP-SRAM1-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-3.
End of enumeration elements list.
PWRCTRL1_LPSRAM_1 : It is enables power control1 to all banks in LP-SRAM-1.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-1.
End of enumeration elements list.
PWRCTRL1_LPSRAM_2 : It is enables power control1 to all banks in LP-SRAM-2.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-2.
End of enumeration elements list.
PWRCTRL1_LPSRAM_3 : It is enables power control1 to all banks in LP-SRAM-3.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-3.
End of enumeration elements list.
PWRCTRL1_LPSRAM_4 : It is enables power control1 to all banks in LP-SRAM-4.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-4.
End of enumeration elements list.
PWRCTRL1_LPSRAM_5 : It is enables power control1 to all banks in LP-SRAM-5.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-5.
End of enumeration elements list.
PWRCTRL1_LPSRAM_6 : It is enables power control1 to all banks in LP-SRAM-6.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-6.
End of enumeration elements list.
PWRCTRL1_LPSRAM_7 : It is enables power control1 to all banks in LP-SRAM-7.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-7.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 10 - 25 (16 bit)
access : read-write
PWRCTRL1_HPSRAM2_1 : It is enables power control1 to all banks in HP-SRAM2-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-1.
End of enumeration elements list.
PWRCTRL1_HPSRAM2_2 : It is enables power control1 to all banks in HP-SRAM2-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-2.
End of enumeration elements list.
PWRCTRL1_HPSRAM2_3 : It is enables power control1 to all banks in HP-SRAM2-3.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-3.
End of enumeration elements list.
PWRCTRL1_HPSRAM2_4 : It is enables power control1 to all banks in HP-SRAM2-4.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-4.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 20 - 51 (32 bit)
access : read-write
Disables power for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL1_HPSRAM1_1 : It is disables power control1 to all banks in HP-SRAM1-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-1.
End of enumeration elements list.
PWRCTRL1_HPSRAM1_2 : It is disables power control1 to all banks in HP-SRAM1-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-2.
End of enumeration elements list.
PWRCTRL1_HPSRAM1_3 : It is disables power control1 to all banks in HP-SRAM1-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-3.
End of enumeration elements list.
PWRCTRL1_LPSRAM_1 : It is disables power control1 to all banks in LP-SRAM-1.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-1.
End of enumeration elements list.
PWRCTRL1_LPSRAM_2 : It is disables power control1 to all banks in LP-SRAM-2.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-2.
End of enumeration elements list.
PWRCTRL1_LPSRAM_3 : It is disables power control1 to all banks in LP-SRAM-3.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-3.
End of enumeration elements list.
PWRCTRL1_LPSRAM_4 : It is disables power control1 to all banks in LP-SRAM-4.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-4.
End of enumeration elements list.
PWRCTRL1_LPSRAM_5 : It is disables power control1 to all banks in LP-SRAM-5.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-5.
End of enumeration elements list.
PWRCTRL1_LPSRAM_6 : It is disables power control1 to all banks in LP-SRAM-6.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-6.
End of enumeration elements list.
PWRCTRL1_LPSRAM_7 : It is disables power control1 to all banks in LP-SRAM-7.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-7.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 10 - 25 (16 bit)
access : read-write
PWRCTRL1_HPSRAM2_1 : It is disables power control1 to all banks in HP-SRAM2-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-1.
End of enumeration elements list.
PWRCTRL1_HPSRAM2_2 : It is disables power to all banks in HP-SRAM2-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-2.
End of enumeration elements list.
PWRCTRL1_HPSRAM2_3 : It is disables power control1 to all banks in HP-SRAM2-3.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-3.
End of enumeration elements list.
PWRCTRL1_HPSRAM2_4 : It is disables power control1 to all banks in HP-SRAM2-4.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-4.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 20 - 51 (32 bit)
access : read-write
Enables power for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL2_HPSRAM1_1 : It is enable power control2 to all banks in HP-SRAM1-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-1.
End of enumeration elements list.
PWRCTRL2_HPSRAM1_2 : It is enable power control2 to all banks in HP-SRAM1-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-2.
End of enumeration elements list.
PWRCTRL2_HPSRAM1_3 : It is enable power control2 to all banks in HP-SRAM1-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-3.
End of enumeration elements list.
PWRCTRL2_LPSRAM_1 : It is enable power control2 to all banks in LP-SRAM-1.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-1.
End of enumeration elements list.
PWRCTRL2_LPSRAM_2 : It is enable power control2 to all banks in LP-SRAM-2.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-2.
End of enumeration elements list.
PWRCTRL2_LPSRAM_3 : It is enable power to all banks in LP-SRAM-3.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-3.
End of enumeration elements list.
PWRCTRL2_LPSRAM_4 : It is enable power control2 to all banks in LP-SRAM-4.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-4.
End of enumeration elements list.
PWRCTRL2_LPSRAM_5 : It is enables power control2 to all banks in LP-SRAM-5.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-5.
End of enumeration elements list.
PWRCTRL2_LPSRAM_6 : It is enables power control2 to all banks in LP-SRAM-6.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-6.
End of enumeration elements list.
PWRCTRL2_LPSRAM_7 : It is enable power control2 to all banks in LP-SRAM-7.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in LP-SRAM-7.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 10 - 25 (16 bit)
access : read-write
PWRCTRL2_HPSRAM2_1 : It is enable power control2 to all banks in HP-SRAM2-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-1.
End of enumeration elements list.
PWRCTRL2_HPSRAM2_2 : It is enable power control2 to all banks in HP-SRAM2-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-2.
End of enumeration elements list.
PWRCTRL2_HPSRAM2_3 : It is enable power control2 to all banks in HP-SRAM2-3.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-3.
End of enumeration elements list.
PWRCTRL2_HPSRAM2_4 : It is enable power control2 to all banks in HP-SRAM2-4.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-4.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 20 - 51 (32 bit)
access : read-write
Disables power for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL2_HPSRAM1_1 : It is disable power control2 to all banks in HP-SRAM1-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-1.
End of enumeration elements list.
PWRCTRL2_HPSRAM1_2 : It is disable power control2 to all banks in HP-SRAM1-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-2.
End of enumeration elements list.
PWRCTRL2_HPSRAM1_3 : It is disable power control2 to all banks in HP-SRAM1-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-3.
End of enumeration elements list.
PWRCTRL2_LPSRAM_1 : It is disable power control2 to all banks in LP-SRAM-1.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-1.
End of enumeration elements list.
PWRCTRL2_LPSRAM_2 : It is disable power control2 to all banks in LP-SRAM-2.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-2.
End of enumeration elements list.
PWRCTRL2_LPSRAM_3 : It is disable power to all banks in LP-SRAM-3.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-3.
End of enumeration elements list.
PWRCTRL2_LPSRAM_4 : It is disable power control2 to all banks in LP-SRAM-4.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-4.
End of enumeration elements list.
PWRCTRL2_LPSRAM_5 : It is disable power control2 to all banks in LP-SRAM-5.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-5.
End of enumeration elements list.
PWRCTRL2_LPSRAM_6 : It is disable power control2 to all banks in LP-SRAM-6.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-6.
End of enumeration elements list.
PWRCTRL2_LPSRAM_7 : It is disable power control2 to all banks in LP-SRAM-7.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in LP-SRAM-7.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 10 - 25 (16 bit)
access : read-write
PWRCTRL2_HPSRAM2_1 : It is disable power control2 to all banks in HP-SRAM2-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-1.
End of enumeration elements list.
PWRCTRL2_HPSRAM2_2 : It is disable power control2 to all banks in HP-SRAM2-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-2.
End of enumeration elements list.
PWRCTRL2_HPSRAM2_3 : It is disable power control2 to all banks in HP-SRAM2-3.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-3.
End of enumeration elements list.
PWRCTRL2_HPSRAM2_4 : It is disable power control2 to all banks in HP-SRAM2-4.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-4.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 20 - 51 (32 bit)
access : read-write
Enables isolation on HP-SRAM, HP-SRAM2 and LP-SRAM input signals.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INP_ISO_HP_SRAM1 : It is enables isolation on inputs for HP-SRAM1 Banks.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables isolation on inputs for HP-SRAM1 Banks.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 1 - 3 (3 bit)
access : read-write
INP_ISO_LP_SRAM : It is enable isolation on inputs for LP-SRAM Banks.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables isolation on inputs for LP-SRAM Banks.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 4 - 19 (16 bit)
access : read-write
INP_ISO_HP_SRAM2 : It is enables isolation on inputs for HP-SRAM2 Banks.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables isolation on inputs for HP-SRAM2 Banks.
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 17 - 48 (32 bit)
access : read-write
Disables isolation on HP-SRAM, HP-SRAM2 and LP-SRAM input signals.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INP_ISO_HP_SRAM1 : It is disables isolation on inputs for HP-SRAM1 Banks.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables isolation on inputs for HP-SRAM1 Banks.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 1 - 3 (3 bit)
access : read-write
INP_ISO_LP_SRAM : It is disable isolation on inputs for LP-SRAM Banks.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables isolation on inputs for LP-SRAM Banks.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 4 - 19 (16 bit)
access : read-write
INP_ISO_HP_SRAM2 : It is disables isolation on inputs for HP-SRAM2 Banks.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables isolation on inputs for HP-SRAM2 Banks.
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 17 - 48 (32 bit)
access : read-write
Enables Deep-Sleep for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DS_HPSRAM1_1_B1 : It is enable deep sleep mode to 1st Bank in HP-SRAM1-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM1-1.
End of enumeration elements list.
DS_HPSRAM1_2_B1 : It is enable deep sleep mode to 1st Bank in HP-SRAM1-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM1-2.
End of enumeration elements list.
DS_HPSRAM1_2_B2 : It is enable deep sleep mode to 2nd Bank in HP-SRAM1-2.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM1-2.
End of enumeration elements list.
DS_HPSRAM1_3_B1 : It is enable deep sleep mode to 1st Bank in HP-SRAM1-3.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM1-3.
End of enumeration elements list.
DS_LPSRAM_1_B1 : It is enable deep sleep mode to 1st Bank in LP-SRAM-1.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-1.
End of enumeration elements list.
DS_LPSRAM_2_B1 : It is enable deep sleep mode to 1st Bank in LP-SRAM-2.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-2.
End of enumeration elements list.
DS_LPSRAM_3_B1 : It is enable deep sleep mode to 1st Bank in LP-SRAM-3.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-3.
End of enumeration elements list.
DS_LPSRAM_4_B1 : It is enables deep sleep mode to 1st Bank in LP-SRAM-4.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-4.
End of enumeration elements list.
DS_LPSRAM_5_B1 : It is enables deep sleep mode to 1st Bank in LP-SRAM-5.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-5.
End of enumeration elements list.
DS_LPSRAM_5_B2 : It is enables deep sleep mode to 2nd Bank in LP-SRAM-5.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in LP-SRAM-5.
End of enumeration elements list.
DS_LPSRAM_6_B1 : It is enables deep sleep mode to 1st Bank in LP-SRAM-6.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_6_B2 : It is enables deep sleep mode to 2nd Bank in LP-SRAM-6.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_6_B3 : It is enables deep sleep mode to 3rd Bank in LP-SRAM-6.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 3rd Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_6_B4 : It is enables deep sleep mode to 4th Bank in LP-SRAM-6.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 4th Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_7_B1 : It is enables deep sleep mode to 1st Bank in LP-SRAM-7.
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-7.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 15 - 30 (16 bit)
access : read-write
DS_HPSRAM2_1_B1 : It is enables deep sleep mode to 1st Bank in HP-SRAM2-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-1.
End of enumeration elements list.
DS_HPSRAM2_2_B1 : It is enables deep sleep mode to 1st Bank in HP-SRAM2-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-2.
End of enumeration elements list.
DS_HPSRAM2_2_B2 : It is enables deep sleep mode to 2nd Bank in HP-SRAM2-2.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM2-2.
End of enumeration elements list.
DS_HPSRAM2_3_B1 : It is enables deep sleep mode to 1st Bank in HP-SRAM2-3.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B2 : It is enables deep sleep mode to 2nd Bank in HP-SRAM2-3.
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B3 : It is enables deep sleep mode to 3rd Bank in HP-SRAM2-3.
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 3rd Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B4 : It is enables deep sleep mode to 4th Bank in HP-SRAM2-3.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 4th Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B5 : It is enables deep sleep mode to 5th Bank in HP-SRAM2-3.
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 5th Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_4_B1 : It is enables deep sleep mode to 1st Bank in HP-SRAM2-4.
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-4.
End of enumeration elements list.
DS_HPSRAM2_4_B2 : It is enables deep sleep mode to 2nd Bank in HP-SRAM2-4.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM2-4.
End of enumeration elements list.
DS_HPSRAM2_4_B3 : It is enables deep sleep mode to 3rd Bank in HP-SRAM2-4.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 3rd Bank in HP-SRAM2-4.
End of enumeration elements list.
DS_HPSRAM2_4_B4 : It is enables deep sleep mode to 4th Bank in HP-SRAM2-4.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 4th Bank in HP-SRAM2-4.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 28 - 59 (32 bit)
access : read-write
Disables Deep-Sleep for HP-SRAM, HP-SRAM2 and LP-SRAM domains
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DS_HPSRAM1_1_B1 : It is disable deep sleep mode to 1st Bank in HP-SRAM1-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM1-1.
End of enumeration elements list.
DS_HPSRAM1_2_B1 : It is disable deep sleep mode to 1st Bank in HP-SRAM1-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM1-2.
End of enumeration elements list.
DS_HPSRAM1_2_B2 : It is disable deep sleep mode to 2nd Bank in HP-SRAM1-2.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM1-2.
End of enumeration elements list.
DS_HPSRAM1_3_B1 : It is disable deep sleep mode to 1st Bank in HP-SRAM1-3.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM1-3.
End of enumeration elements list.
DS_LPSRAM_1_B1 : It is disable deep sleep mode to 1st Bank in LP-SRAM-1.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-1.
End of enumeration elements list.
DS_LPSRAM_2_B1 : It is disable deep sleep mode to 1st Bank in LP-SRAM-2.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-2.
End of enumeration elements list.
DS_LPSRAM_3_B1 : It is disable deep sleep mode to 1st Bank in LP-SRAM-3.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-3.
End of enumeration elements list.
DS_LPSRAM_4_B1 : It is disable deep sleep mode to 1st Bank in LP-SRAM-4.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-4.
End of enumeration elements list.
DS_LPSRAM_5_B1 : It is disable deep sleep mode to 1st Bank in LP-SRAM-5.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-5.
End of enumeration elements list.
DS_LPSRAM_5_B2 : It is disable deep sleep mode to 2nd Bank in LP-SRAM-5.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in LP-SRAM-5.
End of enumeration elements list.
DS_LPSRAM_6_B1 : It is disable deep sleep mode to 1st Bank in LP-SRAM-6.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_6_B2 : It is disable deep sleep mode to 2nd Bank in LP-SRAM-6.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_6_B3 : It is disable deep sleep mode to 3rd Bank in LP-SRAM-6.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 3rd Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_6_B4 : It is disable deep sleep mode to 4th Bank in LP-SRAM-6.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 4th Bank in LP-SRAM-6.
End of enumeration elements list.
DS_LPSRAM_7_B1 : It is disable deep sleep mode to 1st Bank in LP-SRAM-7.
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-7.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 15 - 30 (16 bit)
access : read-write
DS_HPSRAM2_1_B1 : It is disable deep sleep mode to 1st Bank in HP-SRAM2-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM2-1.
End of enumeration elements list.
DS_HPSRAM2_2_B1 : It is disable deep sleep mode to 1st Bank in HP-SRAM2-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disable deep sleep mode to 1st Bank in HP-SRAM2-2.
End of enumeration elements list.
DS_HPSRAM2_2_B2 : It is disable deep sleep mode to 2nd Bank in HP-SRAM2-2.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM2-2.
End of enumeration elements list.
DS_HPSRAM2_3_B1 : It is disable deep sleep mode to 1st Bank in HP-SRAM2-3.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B2 : It is disable deep sleep mode to 2nd Bank in HP-SRAM2-3.
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B3 : It is disable deep sleep mode to 3rd Bank in HP-SRAM2-3.
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 3rd Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B4 : It is disable deep sleep mode to 4th Bank in HP-SRAM2-3.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 4th Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_3_B5 : It is disable deep sleep mode to 5th Bank in HP-SRAM2-3.
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 5th Bank in HP-SRAM2-3.
End of enumeration elements list.
DS_HPSRAM2_4_B1 : It is disable deep sleep mode to 1st Bank in HP-SRAM2-4.
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM2-4.
End of enumeration elements list.
DS_HPSRAM2_4_B2 : It is disable deep sleep mode to 2nd Bank in HP-SRAM2-4.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM2-4.
End of enumeration elements list.
DS_HPSRAM2_4_B3 : It is disable deep sleep mode to 3rd Bank in HP-SRAM2-4.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 3rd Bank in HP-SRAM2-4.
End of enumeration elements list.
DS_HPSRAM2_4_B4 : It is disable deep sleep mode to 4th Bank in HP-SRAM2-4.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 4th Bank in HP-SRAM2-4.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 28 - 59 (32 bit)
access : read-write
Isolation Configuration for Ultra Low-Power Mode of the processor (PS2 State)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULP_ISOLATION_CTRL : Writing 0xAAAA to this provides immediate trigger to SHIP mode.
bits : 0 - 5 (6 bit)
access : write-only
Enumeration:
00 : Disable
Writing 'h00 to this disables Isolation between Low-Voltage and HIGH VOLTAGE Domains.
0x3F : Enable
Writing 'h3F to this enables Isolation between Low-Voltage and HIGH VOLTAGE Domains
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 6 - 37 (32 bit)
access : read-write
Enables power for ULP-PERIPHERALS domains
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 17 (18 bit)
access : read-write
PWRCTRL_TIMER : It is enable power to TIMER
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the TIMER.
End of enumeration elements list.
PWRCTRL_TOUCH : It is enable power to TOUCH
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the TOUCH.
End of enumeration elements list.
PWRCTRL_VAD : It is enable power to TOUCH
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the VAD.
End of enumeration elements list.
PWRCTRL_UART : It is enable power to UART
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the UART.
End of enumeration elements list.
PWRCTRL_SSI : It is enable power to SPI/SSI
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the SPI/SSI.
End of enumeration elements list.
PWRCTRL_I2S : It is enable power to SPI/SSI
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the I2S.
End of enumeration elements list.
PWRCTRL_I2C : It is enable power to I2C
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the I2C.
End of enumeration elements list.
PWRCTRL_ADC_DAC : It is enable power to ADC/DAC
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the ADC/DAC.
End of enumeration elements list.
PWRCTRL_IR : It is enable power to IR
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the IR.
End of enumeration elements list.
PWRCTRL_DMA : It is enable power to IR
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the DMA.
End of enumeration elements list.
PWRCTRL_FIM : It is enable power to FIM
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the FIM.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 29 - 60 (32 bit)
access : read-write
Enables power for ULP-PERIPHERALS domains
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 17 (18 bit)
access : read-write
PWRCTRL_TIMER : It is disable power to TIMER
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the TIMER.
End of enumeration elements list.
PWRCTRL_TOUCH : It is disable power to TOUCH
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the TOUCH.
End of enumeration elements list.
PWRCTRL_VAD : It is disable power to TOUCH
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the VAD.
End of enumeration elements list.
PWRCTRL_UART : It is disable power to UART
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the UART.
End of enumeration elements list.
PWRCTRL_SSI : It is disable power to SPI/SSI
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the SPI/SSI.
End of enumeration elements list.
PWRCTRL_I2S : It is disable power to SPI/SSI
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the I2S.
End of enumeration elements list.
PWRCTRL_I2C : It is disable power to I2C
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the I2C.
End of enumeration elements list.
PWRCTRL_ADC_DAC : It is disable power to ADC/DAC
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the ADC/DAC.
End of enumeration elements list.
PWRCTRL_IR : It is disable power to IR
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the IR.
End of enumeration elements list.
PWRCTRL_DMA : It is disable power to IR
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the DMA.
End of enumeration elements list.
PWRCTRL_FIM : It is disable power to FIM
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the FIM.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 29 - 60 (32 bit)
access : read-write
Enables power for ULP-PERIPHERALS domains
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL1_ULPSRAM_1 : It is enable power to all Banks in ULP-SRAM-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-1.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_2 : It is enable power to all Banks in ULP-SRAM-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-2.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_3 : It is enable power to all Banks in ULP-SRAM-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-3.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_4 : It is enable power to all Banks in ULP-SRAM-4.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-4.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_5 : It is enable power to all Banks in ULP-SRAM-5.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-5.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_6 : It is enable power to all Banks in ULP-SRAM-6.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-6.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_7 : It is enable power to all Banks in ULP-SRAM-7.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-7.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_8 : It is enable power to all Banks in ULP-SRAM-8.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-8.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 8 - 39 (32 bit)
access : read-write
Disables power for ULP-SRAM domains.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL1_ULPSRAM_1 : It is disable power to all Banks in ULP-SRAM-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-1.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_2 : It is disable power to all Banks in ULP-SRAM-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-2.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_3 : It is disable power to all Banks in ULP-SRAM-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-3.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_4 : It is disable power to all Banks in ULP-SRAM-4.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-4.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_5 : It is disable power to all Banks in ULP-SRAM-5.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-5.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_6 : It is disable power to all Banks in ULP-SRAM-6.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-6.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_7 : It is disable power to all Banks in ULP-SRAM-7.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-7.
End of enumeration elements list.
PWRCTRL1_ULPSRAM_8 : It is disable power to all Banks in ULP-SRAM-8.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disable power to all Banks in ULP-SRAM-8.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 8 - 39 (32 bit)
access : read-write
Enables power for ULP-SRAM domains.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 15 (16 bit)
access : read-write
DS_ULPSRAM_1_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-1.
End of enumeration elements list.
DS_ULPSRAM_2_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-2.
End of enumeration elements list.
DS_ULPSRAM_3_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-3.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-3.
End of enumeration elements list.
DS_ULPSRAM_4_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-4.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-4.
End of enumeration elements list.
DS_ULPSRAM_5_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-5.
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-5.
End of enumeration elements list.
DS_ULPSRAM_6_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-6.
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-6.
End of enumeration elements list.
DS_ULPSRAM_7_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-7.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-7.
End of enumeration elements list.
DS_ULPSRAM_8_B1 : It is enable deep sleep mode to 1st Bank in ULP-SRAM-8
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-8.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 24 - 55 (32 bit)
access : read-write
Disables power for ULP-SRAM domains.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 15 (16 bit)
access : read-write
DS_ULPSRAM_1_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-1.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-1.
End of enumeration elements list.
DS_ULPSRAM_2_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-2.
End of enumeration elements list.
DS_ULPSRAM_3_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-3.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-3.
End of enumeration elements list.
DS_ULPSRAM_4_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-4.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-4.
End of enumeration elements list.
DS_ULPSRAM_5_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-5.
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-5.
End of enumeration elements list.
DS_ULPSRAM_6_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-6.
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-6.
End of enumeration elements list.
DS_ULPSRAM_7_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-7.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-7.
End of enumeration elements list.
DS_ULPSRAM_8_B1 : It is disable deep sleep mode to 1st Bank in ULP-SRAM-8
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-8.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 24 - 55 (32 bit)
access : read-write
Enables Deep-Sleep for ULP-SRAM domains.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL2_ULPSRAM_1 : It is enable power control2 to all Banks in ULP-SRAM-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-2.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_2 : It is enable power control2 to all Banks in ULP-SRAM-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-2.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_3 : It is enable power control2 to all Banks in ULP-SRAM-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-3.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_4 : It is enable power control2 to all Banks in ULP-SRAM-4.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-4.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_5 : It is enable power control2 to all Banks in ULP-SRAM-5.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-5.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_6 : It is enable power control2 to all Banks in ULP-SRAM-6.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-6.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_7 : It is enable power control2 to all Banks in ULP-SRAM-7.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-7.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_8 : It is enable power control2 to all Banks in ULP-SRAM-8.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-8.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 8 - 39 (32 bit)
access : read-write
Disables Deep-Sleep for ULP-SRAM domains
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWRCTRL2_ULPSRAM_1 : It is disable power control2 to all Banks in ULP-SRAM-1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-2.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_2 : It is disable power control2 to all Banks in ULP-SRAM-2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-2.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_3 : It is disable power control2 to all Banks in ULP-SRAM-3.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-3.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_4 : It is disable power control2 to all Banks in ULP-SRAM-4.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-4.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_5 : It is disable power control2 to all Banks in ULP-SRAM-5.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-5.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_6 : It is disable power control2 to all Banks in ULP-SRAM-6.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-6.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_7 : It is disable power control2 to all Banks in ULP-SRAM-7.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-7.
End of enumeration elements list.
PWRCTRL2_ULPSRAM_8 : It is disable power control2 to all Banks in ULP-SRAM-8.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-8.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 8 - 39 (32 bit)
access : read-write
Enables power for APPLICATIONS, HIGH SPEED INTERFACES, HP-PERIPHERALS domains
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 1 (2 bit)
access : read-write
PWRCTRL_SDMEM : Enable Power to SDMEM
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the SDMEM.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 3 - 6 (4 bit)
access : read-write
PWRCTRL_EFUSE : Enable Power to EFUSE
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the EFUSE.
End of enumeration elements list.
PWRCTRL_CCI : Enable Power to CCI
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the CCI.
End of enumeration elements list.
PWRCTRL_PERI_DOMAIN3 : Enable Power to PERI-DOMAIN3.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the PERI-DOMAIN3.
End of enumeration elements list.
PWRCTRL_PERI_DOMAIN2 : Enable Power to PERI-DOMAIN2.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the PERI-DOMAIN2.
End of enumeration elements list.
PWRCTRL_PERI_DOMAIN1 : Enable Power to PERI-DOMAIN1.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the PERI-DOMAIN1.
End of enumeration elements list.
PWRCTRL_DMA : Enable Power to DMA.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the DMA.
End of enumeration elements list.
PWRCTRL_USB : Enable Power to USB.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the USB.
End of enumeration elements list.
PWRCTRL_SDIO_SPI : Enable Power to SDIO-SPI Slave.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the SDIO-SPI Slave.
End of enumeration elements list.
PWRCTRL_ETHERNET : Enable Power to SDIO-SPI Slave.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the ETHERNET.
End of enumeration elements list.
PWRCTRL_QSPI : Enable Power to QSPI.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the QSPI.
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 14 - 28 (15 bit)
access : read-write
PWRCTRL_ICACHE : Enable Power to ICACHE.
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the ICACHE.
End of enumeration elements list.
PWRCTRL_FPU : Enable Power to FPU.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the FPU.
End of enumeration elements list.
PWRCTRL_DEBUG : Enable Power to DEBUG.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the DEBUG.
End of enumeration elements list.
RESERVED4 : It is recommended to write these bits to 0.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 19 - 40 (22 bit)
access : read-write
PWRCTRL_ROM : Enable Power to ROM.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this enables power to the ROM.
End of enumeration elements list.
RESERVED6 : It is recommended to write these bits to 0.
bits : 23 - 54 (32 bit)
access : read-write
Controls power for HIGH-FREQ-PLL domains.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 5 (6 bit)
access : read-write
PWRCTRL_PLL_REG : It is enable power to the PLL Programming Registers.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables power to the PLL Programming Registers.
1 : Enable
Writing 1 to this enables power to the PLL Programming Registers.
End of enumeration elements list.
SOCPLL_VDD13_ISO_EN : This is used for isolation of signals from DC-DC 1.35 to the VBATT supply in SoC-PLL to avoid leakage.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 1 to this enables isolation.
1 : Enable
Writing 0 to this disables isolation.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 8 - 39 (32 bit)
access : read-write
Controls power for DDR-FLASH-DLL domains
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 1 (2 bit)
access : read-write
PWRCTRL_DLL_RX : It is enable power to the Rx section of DLL
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables power to the Rx Section of DLL
1 : Enable
Writing 1 to this enables power to the Rx Section of DLL
End of enumeration elements list.
RESERVED2 : It is not recommended to overwrite the content in this bit.
bits : 3 - 8 (6 bit)
access : read-write
PWRCTRL_DLL_TX : It is enable power to the Tx section of DLL
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this disables power to the Tx Section of DLL
1 : Enable
Writing 1 to this enables power to the Tx Section of DLL
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 7 - 38 (32 bit)
access : read-write
Disables power for APPLICATIONS, HIGH SPEED INTERFACES, HP-PERIPHERALS domains
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 1 (2 bit)
access : read-write
PWRCTRL_SDMEM : Disable Power to SDMEM
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the SDMEM.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 3 - 6 (4 bit)
access : read-write
PWRCTRL_EFUSE : Disable Power to EFUSE
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the EFUSE.
End of enumeration elements list.
PWRCTRL_CCI : Disable Power to CCI
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the CCI.
End of enumeration elements list.
PWRCTRL_PERI_DOMAIN3 : Disable Power to PERI-DOMAIN3.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the PERI-DOMAIN3.
End of enumeration elements list.
PWRCTRL_PERI_DOMAIN2 : Disable Power to PERI-DOMAIN2.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the PERI-DOMAIN2.
End of enumeration elements list.
PWRCTRL_PERI_DOMAIN1 : Disable Power to PERI-DOMAIN1.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the PERI-DOMAIN1.
End of enumeration elements list.
PWRCTRL_DMA : Disable Power to DMA.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the DMA.
End of enumeration elements list.
PWRCTRL_USB : Disable Power to USB.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the USB.
End of enumeration elements list.
PWRCTRL_SDIO_SPI : Disable Power to SDIO-SPI Slave.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the SDIO-SPI Slave.
End of enumeration elements list.
PWRCTRL_ETHERNET : Disable Power to SDIO-SPI Slave.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the ETHERNET.
End of enumeration elements list.
PWRCTRL_QSPI : Disable Power to QSPI.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the QSPI.
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 14 - 28 (15 bit)
access : read-write
PWRCTRL_ICACHE : Disable Power to ICACHE.
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the ICACHE.
End of enumeration elements list.
PWRCTRL_FPU : Disable Power to FPU.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the FPU.
End of enumeration elements list.
PWRCTRL_DEBUG : Disable Power to DEBUG.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the DEBUG.
End of enumeration elements list.
RESERVED4 : It is recommended to write these bits to 0.
bits : 18 - 36 (19 bit)
access : read-write
RESERVED5 : It is recommended to write these bits to 0.
bits : 19 - 40 (22 bit)
access : read-write
PWRCTRL_ROM : Disable Power to ROM.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
Writing 0 to this has no effect.
1 : Enable
Writing 1 to this disables power to the ROM.
End of enumeration elements list.
RESERVED6 : It is recommended to write these bits to 0.
bits : 23 - 54 (32 bit)
access : read-write
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