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ULTRA_LOW_POWER_DOMAINS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

Registers

MCUULP_VBAT_LFCLK_REG


MCUULP_VBAT_LFCLK_REG

Low Frequency Clock Select Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCUULP_VBAT_LFCLK_REG MCUULP_VBAT_LFCLK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCUULP_VBAT_LF_CLK_SEL MCUULP_VBAT_LF_CLK_SWITCHED RESERVED1

MCUULP_VBAT_LF_CLK_SEL : Select the MCU VBAT clock.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

1 : ro_32k_clk

Enable ro 32khz clock

2 : rc_32k_clk

Enable rc 32khz clock

4 : xtal_32k_clk

Enable rc 32khz clock

End of enumeration elements list.

MCUULP_VBAT_LF_CLK_SWITCHED : Status of NPSS Low Frequency Clock Dynamic Clock Mux
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : Enable

Clock got switched and output clock can be used

0 : Disable

Clock switching is in progress

End of enumeration elements list.

RESERVED1 : It is recommended to write these bits to 0.
bits : 4 - 35 (32 bit)
access : read-only



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