Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
Sleep Control Signals and Wakeup source selection
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : It is recommended to write these bits to 0.
bits : 0 - 2 (3 bit)
access : read-write
HP_SRAM1_RETENTION_EN : SRAM retention Control for 64KB of HP-SRAM1
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : disable
Writing 1 to this enables Retention during sleep
1 : enable
Writing 1 to this enables Retention during sleep
End of enumeration elements list.
LP_SRAM_RETENTION_EN : SRAM retention Control for 112KB of LP-SRAM (LP-SRAM-5, LP-SRAM-6, LP-SRAM-7)
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : disable
Writing 1 to this enables Retention during sleep
1 : enable
Writing 1 to this enables Retention during sleep
End of enumeration elements list.
HP_SRAM2_RETENTION_EN : SRAM retention Control for 192KB of HP-SRAM2
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : disable
Writing 1 to this enables Retention during sleep
1 : enable
Writing 1 to this enables Retention during sleep
End of enumeration elements list.
ULP_SRAM_RETENTION_EN : SRAM retention Control for 16KB of ULP-SRAM
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : disable
Writing 1 to this enables Retention during sleep
1 : enable
Writing 1 to this enables Retention during sleep
End of enumeration elements list.
LP_SRAM_16KB_RETENTION_EN : SRAM retention Control for 16KB of LP-SRAM (LP-SRAM-1, LP-SRAM-2, LP-SRAM-3, LP-SRAM-4)
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : disable
Writing 1 to this enables Retention during sleep
1 : enable
Writing 1 to this enables Retention during sleep
End of enumeration elements list.
LDoSoC_ON : It is maintain LDO SOC 1.1 on state
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this maintains LDO SoC 1.1 in OFF state during Sleep.
1 : enable
Writing 1 to this maintains LDO SoC 1.1 in ON state during Sleep.
End of enumeration elements list.
LDOFL_ON : It is maintain LDO FL 1.8 on state
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this maintains LDO FL 1.8 in OFF state during Sleep.
1 : enable
Writing 1 to this maintains LDO FL 1.8 in ON state during Sleep.
End of enumeration elements list.
DCDC_ON : It is maintain DC-DC 1.35 on state
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this maintains LDO FL 1.8 in OFF state during Sleep.
1 : enable
Writing 1 to this maintains LDO FL 1.8 in ON state during Sleep.
End of enumeration elements list.
SKIP_XTAL_WAIT_TIME : It is used to skips the settling time for High Frequency XTAL during wakeup.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this includes the settling time for High Frequency XTAL during wakeup.
1 : enable
Writing 1 to this skips the settling time for High Frequency XTAL during wakeup.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 12 - 27 (16 bit)
access : read-write
RTC_Wakeup : It is enable or disable RTC Interrupt as a Wakeup source
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables RTC Interrupt as a Wakeup source
1 : enable
Writing 1 to this enables RTC Interrupt as a Wakeup source
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 17 - 34 (18 bit)
access : read-write
NWP_Wakeup : It is enable or disable NWP Interrupt as a Wakeup source
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables RTC Interrupt as a Wakeup source
1 : enable
Writing 1 to this enables RTC Interrupt as a Wakeup source
End of enumeration elements list.
RESERVED4 : It is recommended to write these bits to 0.
bits : 19 - 38 (20 bit)
access : read-write
UULP_Vbat_GPIO_Wakeup : It is enable or disable UULP Vbat GPIO Interrupt as a Wakeup source
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables UULP Vbat GPIO Interrupt as a Wakeup source
1 : enable
Writing 1 to this enables UULP Vbat GPIO Interrupt as a Wakeup source
End of enumeration elements list.
CMPR_BOD_BUTTON_Wakeup : It is enable or disable 4x-Comparator/BOD/BUTTON Interrupt as a Wakeup source
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables 4x-Comparator/BOD/BUTTON Interrupt as a Wakeup source
1 : enable
Writing 1 to this enables 4x-Comparator/BOD/BUTTON Interrupt as a Wakeup source
End of enumeration elements list.
WuRx_Wakeup : It is enable or disable wake-Fi Rx Interrupt as a Wakeup source
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Wake-Fi Rx Interrupt as a Wakeup source.
1 : enable
Writing 1 to this enables Wake-Fi Rx Interrupt as a Wakeup source.
End of enumeration elements list.
RESERVED6 : It is recommended to write these bits to 0.
bits : 23 - 46 (24 bit)
access : read-write
ULP_Peripheral_Wakeup : It is enable or disable ULP Peripheral Interrupt as a Wakeup source
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables ULP Peripheral Interrupt as a Wakeup source
1 : enable
Writing 1 to this enables ULP Peripheral Interrupt as a Wakeup source
End of enumeration elements list.
SDC_Wakeup : It is enable or disable Sensor Data Collector Interrupt as a Wakeup source.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Sensor Data Collector Interrupt as a Wakeup source
1 : enable
Writing 1 to this enables Sensor Data Collector Interrupt as a Wakeup source
End of enumeration elements list.
Alarm_Wakeup : It is enable or disable ALARM Interrupt as a Wakeup source.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables ALARM Interrupt as a Wakeup source.
1 : enable
Writing 1 to this enables ALARM Interrupt as a Wakeup source.
End of enumeration elements list.
Second_Wakeup : It is enable or disable Second Interrupt as a Wakeup source
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Second Interrupt as a Wakeup source.
1 : enable
Writing 1 to this enables Second Interrupt as a Wakeup source
End of enumeration elements list.
MilliSecond_Wakeup : It is enable or disable Milli-Second Interrupt as a Wakeup source
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Milli-Second Interrupt as a Wakeup source.
1 : enable
Writing 1 to this enables Milli-Second Interrupt as a Wakeup source.
End of enumeration elements list.
WDT_Wakeup : It is enable or disable WDT Interrupt as a Wakeup source.
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables WDT Interrupt as a Wakeup source.
1 : enable
Writing 1 to this enables WDT Interrupt as a Wakeup source.
End of enumeration elements list.
ULP_Peripheral_Sleep : It is enable or disable ULP Peripheral Interrupt as a Sleep source.
bits : 30 - 60 (31 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables ULP Peripheral Interrupt as a Sleep source.
1 : enable
Writing 1 to this enables ULP Peripheral Interrupt as a Sleep source.
End of enumeration elements list.
RESERVED7 : It is recommended to write these bits to 0.
bits : 31 - 62 (32 bit)
access : read-write
Power Control and Delay Configuration for Ultra Low-Power Mode of the processor (PS2 State)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DCDC_LDoSoC_OFF_TIME : Configures the time for switching OFF the LDO SoC 1.1 and the DC-DC 1.35 during transition from PS2 to PS4 state.
bits : 0 - 4 (5 bit)
access : read-write
RESERVED1 : It is recommended to write these bits to 0.
bits : 5 - 12 (8 bit)
access : read-write
LDoSoC_ON_TIME : Configures the time for switching ON the LDO SoC 1.1 during transition from PS2 to PS4 state.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : 50
Configure switching 50us ON time of LDO Soc.
1 : 100
Configure switching 100us ON time of LDO Soc.
2 : 200
Configure switching 200us ON time of LDO Soc.
3 : 300
Configure switching 300us ON time of LDO Soc.
4 : 400
Configure switching 400us ON time of LDO Soc.
5 : 500
Configure switching 500us ON time of LDO Soc.
6 : 600
Configure switching 600us ON time of LDO Soc.
7 : 700
Configure switching 700us ON time of LDO Soc.
8 : 800
Configure switching 800us ON time of LDO Soc.
9 : 900
Configure switching 900us ON time of LDO Soc.
10 : 1000
Configure switching 1000us ON time of LDO Soc.
11 : 1100
Configure switching 1100us ON time of LDO Soc.
12 : 1200
Configure switching 1200us ON time of LDO Soc.
13 : 1300
Configure switching 1300us ON time of LDO Soc.
14 : 1400
Configure switching 1400us ON time of LDO Soc.
15 : 1500
Configure switching 1400us ON time of LDO Soc.
End of enumeration elements list.
DCDC_ON_TIME : Configures the time for switching ON the DC-DC 1.35 during transition from PS2 to PS4 state.
bits : 12 - 27 (16 bit)
access : read-write
Enumeration:
0 : 50
Configure switching 50us ON time of DC-DC.
1 : 100
Configure switching 100us ON time of DC-DC.
2 : 200
Configure switching 200us ON time of DC-DC.
3 : 300
Configure switching 300us ON time of DC-DC.
4 : 400
Configure switching 400us ON time of DC-DC.
5 : 500
Configure switching 500us ON time of DC-DC.
6 : 600
Configure switching 600us ON time of DC-DC.
7 : 700
Configure switching 700us ON time of DC-DC.
8 : 800
Configure switching 800us ON time of DC-DC.
9 : 900
Configure switching 900us ON time of DC-DC.
10 : 1000
Configure switching 1000us ON time of DC-DC.
11 : 1100
Configure switching 1100us ON time of DC-DC.
12 : 1200
Configure switching 1200us ON time of DC-DC.
13 : 1300
Configure switching 1300us ON time of DC-DC.
14 : 1400
Configure switching 1400us ON time of DC-DC.
15 : 1500
Configure switching 1400us ON time of DC-DC.
End of enumeration elements list.
LDoSoC_EN : Its used to configures LDO Soc 1.1 ON or OFF state during PS2.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : OFF
Writing 0 to this configures LDO SoC 1.1 in OFF state during PS2.
1 : ON
Writing 1 to this configures LDO SoC 1.1 to ON state during PS2.
End of enumeration elements list.
DCDC_EN : Its used to configures DC-DC 1.35 ON or OFF state during PS2.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : OFF
Writing 0 to this configures DC-DC 1.35 in OFF state during PS2.
1 : ON
Writing 1 to this configures DC-DC 1.35 to ON state during PS2.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 18 - 36 (19 bit)
access : read-write
VOLTAGE_SEL_ULP_PERIPH : Configures the Voltage source to be used for LOW-VOLTAGE-ULPPERIPH Domain in PS2 .
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : 0
DC-DC 0.95.
1 : 1
LDO SoC 1.1
End of enumeration elements list.
VOLTAGE_SEL_PROC : Configures the Voltage source to be used for PROC-DOMAIN Domain in PS2 state.
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : 0
LDO 0.7V
1 : 1
DC-DC 0.95
3 : 3
LDO SoC 1.1
End of enumeration elements list.
VOLTAGE_SEL_LP_SRAM_16KB : Configures the Voltage source to be used for LOW-VOLTAGE-LPRAM-16KB Domain in PS2 state.
bits : 22 - 45 (24 bit)
access : read-write
Enumeration:
0 : 0
LDO 0.7V
1 : 1
DC-DC 0.95
3 : 3
LDO SoC 1.1
End of enumeration elements list.
VOLTAGE_SEL_LP_SRAM : Configures the Voltage source to be used for LOW-VOLTAGE-LPRAM Domain in PS2 state.
bits : 24 - 49 (26 bit)
access : read-write
Enumeration:
0 : 0
RESERVED1
1 : 1
DC-DC 0.95
3 : 3
LDO SoC 1.1
End of enumeration elements list.
VOLTAGE_SEL_ULP_SRAM : Configures the Voltage source to be used for LOW-VOLTAGE-ULPRAM Domain in PS2 state.
bits : 26 - 53 (28 bit)
access : read-write
Enumeration:
0 : 0
RESERVED4
1 : 1
DC-DC 0.95
3 : 3
LDO SoC 1.1
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 28 - 59 (32 bit)
access : read-write
High Frequency Clock Select Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : Reserved1
bits : 0 - 1 (2 bit)
access : read-only
MCUULP_VBAT_HF_CLK_SEL : Select the MCU VBAT clock.
bits : 2 - 6 (5 bit)
access : read-write
Enumeration:
0 : clock_gated
clock gated
1 : ro_20m_clk
Enable rc 20Mhz clock
2 : rc_32m_clk
Enable rc 20Mhz clock
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 5 - 19 (15 bit)
access : read-only
MCUULP_VBAT_HF_CLK_SWITCHED : Status of NPSS High Frequency Clock Dynamic Clock Mux
bits : 15 - 30 (16 bit)
access : read-only
Enumeration:
1 : Enable
Clock got switched and output clock can be used
0 : Disable
Clock switching is in progress
End of enumeration elements list.
RESERVED3 : It is recommended to write these bits to 0.
bits : 16 - 47 (32 bit)
access : read-only
ULP Clock Oscillators Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RESERVED1 : Reserved1
bits : 0 - 15 (16 bit)
access : read-write
RC_32KHZ_CLK_EN : Enable or disable RC 32 KHZ clock
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : Enable
Writing 1 to this enables the RC 32KHz Clock
0 : Disable
Writing 0 to this disables the RC 32KHz Clock
End of enumeration elements list.
RO_32KHZ_CLK_EN : Enable or disable RO 32 KHZ clock
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
1 : Enable
Writing 1 to this enables the RO 32KHz Clock
0 : Disable
Writing 0 to this disables the RO 32KHz Clock
End of enumeration elements list.
XTAL_32KHZ_CLK_EN : Enable or disable XTAL 32KHz Clock
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
1 : Enable
Writing 1 to this enables the XTAL 32KHz Clock
0 : Disable
Writing 0 to this disables the XTAL 32KHz Clock
End of enumeration elements list.
RC_32MHZ_CLK_EN : Enable or disable RC 32MHz Clock
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
1 : Enable
Writing 1 to this enables the XTAL 32KHz Clock
0 : Disable
Writing 0 to this disables the XTAL 32KHz Clock
End of enumeration elements list.
RO_HF_CLK_EN : Enable or disable RO High-Frequency Clock
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
1 : Enable
Writing 1 to this enables the RO High-Frequency Clock
0 : Disable
Writing 0 to this disables the RO High-Frequency Clock
End of enumeration elements list.
DOUBLER_CLK_EN : Enable or disable DOUBLER Clock
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
1 : Enable
Writing 1 to this enables the Doubler Clock
0 : Disable
Writing 0 to this disables the Doubler Clock
End of enumeration elements list.
XTAL_40MHZ_CLK_EN : Enable or disable XTAL 40MHZ Clock
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
1 : Enable
Writing 1 to this enables the XTAL-40MHz Clock
0 : Disable
Writing 0 to this disables the XTAL-40MHz Clock
End of enumeration elements list.
RESERVED2 : RESERVED2
bits : 23 - 54 (32 bit)
access : read-write
Power Domains Controlled by Sleep FSM.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EN_WDT_SLEEP : Its enable or disable WDT during Sleep/Shutdown states.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this enables WDT during Sleep/Shutdown states.
1 : enable
Writing 1 to this enables WDT during Sleep/Shutdown states.
End of enumeration elements list.
WAKEFI_RX_EN : Its enable or disable detection of On-Air Pattern using Wake-Fi Rx.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables detection of On-Air Pattern using Wake-Fi Rx.
1 : enable
Writing 1 to this enables detection of On-Air Pattern using Wake-Fi Rx.
End of enumeration elements list.
RESET_BFF_EN : Its enable or disable reset of Power Domain Control Battery FF's on wakeup.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables reset of Power Domain Control Battery FF's on wakeup.
1 : enable
Writing 1 to this enables reset of Power Domain Control Battery FF's on wakeup
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 3 - 18 (16 bit)
access : read-write
PWRCTRL_LP_FSM : Its enable or disable Power to Low-Power FSM.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Power to Low-Power FSM.
1 : enable
Writing 1 to this enables Power to Low-Power FSM.
End of enumeration elements list.
PWRCTRL_TIMESTAMP : Its enable or disable Power to TIMESTAMP.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Power to TIMESTAMP.
1 : enable
Writing 1 to this enables Power to TIMESTAMP.
End of enumeration elements list.
PWRCTRL_DS_TIMER : Its enable or disable Power to DEEP SLEEP Timer.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Power to DEEP SLEEP Timer.
1 : enable
Writing 1 to this enables Power to DEEP SLEEP Timer.
End of enumeration elements list.
PWRCTRL_RETEN : Its enable or disable Power to Retention Flops during SHIP state.These Flops are used for storing Chip Configuration.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables Power to Retention Flops during SHIP state. These Flops are used for storing Chip Configuration.
1 : enable
Writing 1 to this enables Power to Retention Flops during SHIP state. These Flops are used for storing Chip Configuration.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 20 - 51 (32 bit)
access : read-write
Configuration for Ultra Low-Power Mode of the processor (PS2 State)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULP_MODE_VOLT_SWITCH : Enables voltage switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables voltage switching for PS2-PS4/PS3 state transition
1 : enable
Writing 1 to this enables voltage switching for PS4/PS3-PS2 state transition.
End of enumeration elements list.
ULP_MODE_FUNC_SWITCH : Enable functional switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables functional switching for PS2-PS4/PS3 state transition
1 : enable
Writing 1 to this enables functional switching for PS4/PS3-PS2 state transition.
End of enumeration elements list.
ULP_MODE_MEM_CONFIG : Its enable or disable maximum of 32KB of LP-SRAM for operation in PS2 state
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this enables a maximum of 128KB of LP-SRAM for operation in PS2 state.
1 : enable
Writing 1 to this enables a maximum of 32KB of LP-SRAM for operation in PS2 state.
End of enumeration elements list.
RESERVED1 : It is recommended to write these bits to 0.
bits : 3 - 18 (16 bit)
access : read-write
BGPMU_SAMPLING_EN : Controls the mode of Band-Gap for DC-DC 1.35 during PS2 state.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : disable
Writing 0 to this disables sampling mode of Band-Gap. This is described in Power Management Section.
1 : enable
Writing 1 to this enables sampling mode of Band-Gap. This is described in Power Management Section.
End of enumeration elements list.
RESERVED2 : It is recommended to write these bits to 0.
bits : 17 - 48 (32 bit)
access : read-write
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