\n
address_offset : 0x0 Bytes (0x0)
size : 0x124 byte (0x0)
mem_usage : registers
protection :
Configuration Register 0_0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CLK_SEL1 : Mux select for clock_mux_1
bits : 0 - 1 (2 bit)
access : read-write
PRE_SCALAR_1 : Division factor for clock divider
bits : 2 - 11 (10 bit)
access : read-write
PRE_SCALAR_2 : Division factor for clock divider
bits : 10 - 23 (14 bit)
access : read-write
CLK_SEL2 : Mux select for clock_mux_2
bits : 14 - 28 (15 bit)
access : read-write
CTS_STATIC_CLK_EN : Enable static for capacitive touch sensor
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : disable
Clocks are gated
1 : enable
Clocks are not gated
End of enumeration elements list.
FIFO_AFULL_THRLD : Threshold for fifo afull
bits : 16 - 37 (22 bit)
access : read-write
FIFO_AEMPTY_THRLD : Threshold for fifo aempty
bits : 22 - 49 (28 bit)
access : read-write
FIFO_EMPTY : FIFO empty status bit
bits : 28 - 56 (29 bit)
access : read-only
RESERVED1 : Reserved1
bits : 29 - 60 (32 bit)
access : read-only
Configuration Register 1_1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
POLYNOMIAL_LEN : Length of polynomial
bits : 0 - 1 (2 bit)
access : read-write
SEED_LOAD : Seed of polynomial
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : disable
loading of seed is not allowed
1 : enable
to load the seed
End of enumeration elements list.
BUFFER_DELAY : Delay of buffer. Delay programmed will be equal to delay in nano seconds. Max delay value is 32.Default delay should be programmed before using Capacitive touch sensor module.
bits : 3 - 10 (8 bit)
access : read-write
WAKE_UP_ACK : Ack for wake up interrupt. This is a level signal. To acknowledge wake up , set this bit to one and reset it .
bits : 8 - 16 (9 bit)
access : read-write
ENABLE1 : Enable signal
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : disable
disable the cap sensor module
1 : enable
enable the cap sensor module
End of enumeration elements list.
SOFT_RESET_2 : Reset the FIFO write and FIFO read occupancy pointers
bits : 10 - 20 (11 bit)
access : read-write
CNT_ONEHOT_MODE : Continuous or One hot mode
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : One_hot
disable the cap sensor module
1 : Continuous
enable the cap sensor module
End of enumeration elements list.
SAMPLE_MODE : Select bits for FIFO write and FIFO average
bits : 12 - 25 (14 bit)
access : read-write
RESET_WR_FIFO : Resets the signal fifo_wr_int
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : Reset
Reset
1 : Out_of_reset
Out of reset
End of enumeration elements list.
BYPASS : Bypass signal
bits : 15 - 30 (16 bit)
access : write-only
Enumeration:
0 : Disable
Use Random number generator output bit as input to Non-Overlapping stream generator.
1 : Enable
Bypass the Random number generator output to the Non-overlapping stream generator and to give clock as input to the Non-Overlapping stream generator.
End of enumeration elements list.
BIT_SEL : Selects different set of 12 bits to be stored in FIFO
bits : 16 - 33 (18 bit)
access : read-write
RESERVED1 : Reserved1
bits : 18 - 36 (19 bit)
access : read-write
EXT_TRIG_EN : Select bit for NPSS clock or Enable
bits : 19 - 38 (20 bit)
access : write-only
Enumeration:
0 : Enable
Enable
1 : Clock
NPSS clock
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 20 - 51 (32 bit)
access : read-write
Configuration Register 1_2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PWM_ON_PERIOD : PWM ON period
bits : 0 - 15 (16 bit)
access : read-write
PWM_OFF_PERIOD : PWM OFF period
bits : 16 - 47 (32 bit)
access : read-write
Configuration Register 1_3
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PRS_SEED : Pseudo random generator (PRS) seed value
bits : 0 - 31 (32 bit)
access : read-write
Configuration Register 1_4
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PRS_POLY : Polynomial programming register for PRS generator
bits : 0 - 31 (32 bit)
access : read-write
Configuration Register 1_5
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INTER_SENSOR_DELAY : Inter-sensor scan delay value
bits : 0 - 15 (16 bit)
access : read-write
N_SAMPLE_COUNT : Number of repetitions of sensor scan
bits : 16 - 47 (32 bit)
access : read-write
Configuration Register 1_6
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SENSOR_CFG : Register of scan controller containing the programmed bit map
bits : 0 - 31 (32 bit)
access : read-write
Configuration Register 1_7
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
VALID_SENSORS : Value of number of sensors valid in the bit map
bits : 0 - 3 (4 bit)
access : read-write
RESERVED1 : Reserved1
bits : 4 - 9 (6 bit)
access : read-write
VREF_SEL : Enable for Vref programmed
bits : 6 - 12 (7 bit)
access : read-write
MASK_FIFO_AFULL_INTR : Wake up interrupt and fifo_afull_intr are ORed and given as a single interrupt to the processor.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : Masked
fifo_afull_intr is masked
0 : Unmaked
fifo_afull_intr is unmasked
End of enumeration elements list.
RESERVED2 : Reserved2
bits : 8 - 19 (12 bit)
access : read-write
REF_VOLT_CONFIG : This is given as an input voltage to analog model as comparator reference voltage.
bits : 12 - 26 (15 bit)
access : read-write
WAKEUP_MODE : Select bit for high/low mode.
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
1 : Greater_Than
Wakeup if count is greater than threshold
0 : Less_Than
Wakeup if count is lesser than threshold
End of enumeration elements list.
WAKE_UP_THRESHOLD : Wakeup threshold.
bits : 16 - 47 (32 bit)
access : read-write
Configuration Register 1_8
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
PRS_STATE : Current state of PRS
bits : 0 - 31 (32 bit)
access : read-only
Configuration Register 1_9
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TRIG_DIV : Allows one pulse for every 'trig_div' no. of pulses of 1 ms clock
bits : 0 - 9 (10 bit)
access : read-write
RESERVED1 : Reserved1
bits : 10 - 41 (32 bit)
access : read-write
FIFO Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO : Used for FIFO reads and write operations
bits : 0 - 31 (32 bit)
access : read-write
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