SMIH_SDMA_SYSTEM_ADDRESS_REGISTER

SMIH_RESPONSE_REGISTER0

SMIH_RESPONSE_REGISTER1

SMIH_RESPONSE_REGISTER2

SMIH_RESPONSE_REGISTER3

SMIH_RESPONSE_REGISTER4

SMIH_RESPONSE_REGISTER5

SMIH_RESPONSE_REGISTER6

SMIH_RESPONSE_REGISTER7

SMIH_BUFFER_DATA_PORT_REGISTER

SMIH_PRESENT_STATE_REGISTER

SMIH_HOST_CONTROL_1_REGISTER

SMIH_POWER_CONTROL_REGISTER

SMIH_BLOCK_GAP_CONTROL_REGISTER

SMIH_WAKE_UP_CONTROL_REGISTER

SMIH_CLOCK_CONTROL_REGISTER

SMIH_TIMEOUT_CONTROL_REGISTER

SMIH_SOFTWARE_RESET_REGISTER

SMIH_NORMAL_INTERRUPT_STATUS_REGISTER

SMIH_ERROR_INTERRUPT_STATUS_REGISTER

SMIH_NORMAL_INTERRUPT_STATUS_ENABLE_REGISTER

SMIH_ERROR_INTERRUPT_STATUS_ENABLE_REGISTER

SMIH_NORMAL_INTERRUPT_SIGNAL_ENABLE_REGISTER

SMIH_ERROR_INTERRUPT_SIGNAL_ENABLE_REGISTER

SMIH_AUTO_CMD_ERROR_STATUS_REGISTER

SMIH_HOST_CONTROL_2_REGISTER

SMIH_BLOCK_SIZE_REGISTER

SMIH_CAPABILITIES_REGISTER

SMIH_MAXIMUM_CURRENT_CAPABILITIES_REGISTER

SMIH_ADMA_ERROR_STATUS_REGISTER

SMIH_ADMA_SYSTEM_ADDRESS0_REGISTER

SMIH_ADMA_SYSTEM_ADDRESS1_REGISTER

SMIH_ADMA_SYSTEM_ADDRESS2_REGISTER

SMIH_ADMA_SYSTEM_ADDRESS3_REGISTER

SMIH_BLOCK_COUNT_REGISTER

SMIH_PRESET_VALUE_REGISTER0

SMIH_PRESET_VALUE_REGISTER1

SMIH_PRESET_VALUE_REGISTER2

SMIH_PRESET_VALUE_REGISTER3

SMIH_PRESET_VALUE_REGISTER4

SMIH_PRESET_VALUE_REGISTER5

SMIH_PRESET_VALUE_REGISTER6

SMIH_PRESET_VALUE_REGISTER7

SMIH_ARGUMENT1_REGISTER

TRANSFER_MODE_REGISTER

SMIH_COMMAND_REGISTER

SMIH_TX_TUNE_REGISTER

SMIH_RX_TUNE_REGISTER

SMIH_DS_TUNE_REGISTER

SMIH_AHB_BURST_SIZE_REGISTER

SMIH_SDH_REVISION_ID_REGISTER

SMIH_SLOT_INTERRUPT_STATUS_REGISTER

SMIH_HOST_CONTROLLER_VERSION_REGISTER

SDMA_SYSTEM_ADDRESS_OR_ARGUMENT_2 : This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23.
bits : 0 - 31 (32 bit)
access : read-write

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

COMMAND_RESPONSE : This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
bits : 0 - 15 (16 bit)
access : read-only

BUFFER_DATA : The SMIHC Controller buffer can be accessed through this 32-bit Data Port register.
bits : 0 - 31 (32 bit)
access : read-write

COMMAND_INHIBIT_CMD : If this bit is 0, it indicates the CMD line is not in use and the SMIHC, Controller can issue a SD Command using the CMD line. This bit is set immediately after the Command register (00Fh) is written.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

COMMAND_INHIBIT_DAT : This status bit is generated if either the DAT Line Active or the Read Transfer Active is set to 1., If this bit is 0, it indicates the SMIHC Controller can issue the next SD Command Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type).
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DAT_LINE_ACTIVE : This bit indicates whether one of the DAT line on SD Bus is in use.
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RE_TUNING_REQUEST : Re-Tuning Request.
bits : 3 - 6 (4 bit)
access : read-only

Reserved1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-only

WRITE_TRANSFER_ACTIVE : This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the SMIHC Controller..
bits : 8 - 16 (9 bit)
access : read-only

Enumeration:

End of enumeration elements list.

READ_TRANSFER_ACTIVE : This status is used for detecting completion of a read transfer.
bits : 9 - 18 (10 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFFER_WRITE_ENABLE : This status is used for non-DMA write transfers.The SMIHC Controller can implement multiple buffers to transfer data efficiently. This read only flag indicates if space is available for write data.
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFFER_READ_ENABLE : This status is used for non-DMA read transfers. The SMIHC Controller may implement multiple buffers to transfer data efficiently. This read only flag indicates that valid data exists in the host side.
bits : 11 - 22 (12 bit)
access : read-only

Enumeration:

End of enumeration elements list.

Reserved2 : Reserved2
bits : 12 - 27 (16 bit)
access : read-write

CARD_INSERTED : This bit indicates whether a card has been inserted. The SMIHC Controller shall debounce this signal so that the Host Driver will not need to wait for it to stabilize.
bits : 16 - 32 (17 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CARD_STATE_STABLE : This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable.
bits : 17 - 34 (18 bit)
access : read-only

CARD_DETECT_PIN_LEVEL : This bit reflects the inverse value of the SDCD pin.Debouncing is not performed on this bit. This bit may be valid when Card State Stable is set to 1, but it is not guaranteed because of propagation delay.
bits : 18 - 36 (19 bit)
access : read-only

Reserved3 : Reserved3
bits : 19 - 38 (20 bit)
access : read-write

DAT_LINE_SIGNAL_LEVEL : This status is used to check the DAT line level to recover from errors and for debugging.
bits : 20 - 43 (24 bit)
access : read-only

CMD_LINE_SIGNAL_LEVEL : This status is used to check the CMD line level to recover from errors and for debugging.
bits : 24 - 48 (25 bit)
access : read-only

Reserved4 : Reserved4
bits : 25 - 56 (32 bit)
access : read-write

LED_CONTROL : This bit is used to caution the user not to remove the card while the SD card is being accessed.If the software is going to issue multiple SD commands, this bit can be set during all these transactions.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_TRANSFER_WIDTH : This bit selects the data width of the SMIHC Controller.The Host Driver shall set it to match the data width of the SD card.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIGH_SPEED_ENABLE : This bit is optional. Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_SELECT : One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXTENDED_DATA_TRANSFER_WIDTH : This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_DETECT_TEST_LEVEL : This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_DETECT_SIGNAL_SELECTION : This bit selects source for the card detection.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SD_BUS_POWER : Before setting this bit, the SD Host Driver shall set SD Bus Voltage Select. If the SMIHC Controller detects the No Card state, this bit shall be cleared.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SD_BUS_VOLTAGE_SELECT : By setting these bits, the Host Driver selects the voltage level for the SD card. Before setting this register, the Host Driver shall check the Voltage.
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMIH_OD_PP : This bit is used only in MMC mode.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMIH_RST_N : External Hardware reset, used only in MMC mode
bits : 5 - 10 (6 bit)
access : read-write

Reserved1 : Reserved1
bits : 6 - 13 (8 bit)
access : read-write

STOP_AT_BLOCK_GAP_REQUEST : This bit is used to stop executing read and write transaction at the next block gap for non-DMA, SDMA and ADMA transfers. The Host Driver
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CONTINUE_REQUEST : This bit is used to restart a transaction which was stopped using Stop At Block Gap request. To cancel stop at block gap Stop At Block Gap to Zero And set this bit to restart the transfer.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

READ_WAIT_CONTROL : The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the DAT[2] line.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTERRUPT_AT_BLOCK_GAP : This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Reserved1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write

WAKE_UP_EVENT_ENABLE_ON_CARD_INTERRUPT : This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

WAKE_UP_EVENT_ENABLE_ON_SD_CARD_INSERTION : This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS (Wake Up Support) in CIS does not affect this bit.
bits : 1 - 2 (2 bit)
access : read-write

WAKE_UP_EVENT_ENABLE_ON_SD_CARD_REMOVAL : This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register.FN_WUS (Wake Up Support) in CIS does not affect this bit.
bits : 2 - 4 (3 bit)
access : read-write

Reserved1 : Reserved1
bits : 3 - 10 (8 bit)
access : read-write

INTERNAL_CLOCK_ENABLE : This bit is set to 0 when the Host Driver is not using the SMIHC Controller or the SMIHC Controller awaits a wakeup interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTERNAL_CLOCK_STABLE : This bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in this register to 1.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SD_CLOCK_ENABLE : The SMIHC Controller shall stop SDCLK when writing this bit to 0.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Reserved1 : Reserved1
bits : 3 - 7 (5 bit)
access : read-write

CLOCK_GENERATOR_SELECT : This bit is used to select the clock generator mode in SDCLK Frequency select
bits : 5 - 10 (6 bit)
access : read-write

UPPER_BITS_OF_SDCLK_FREQUENCY_SELECT : PE_SMIH Controller shall support these bits to expand SDCLK Frequency Select to 10-bit
bits : 6 - 13 (8 bit)
access : read-write

SDCLK_FREQUENCY_SELECT : This register is used to select the frequency of SDCLK pin.
bits : 8 - 23 (16 bit)
access : read-write

DATA_TIMEOUT_COUNTER_VALUE : This value determines the interval by which DAT line timeouts are detected.
bits : 0 - 3 (4 bit)
access : read-write

Reserved1 : Reserved1
bits : 4 - 11 (8 bit)
access : read-write

SOFTWARE_RESET_FOR_ALL : This reset affects the entire SMIHC Controller except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SOFTWARE_RESET_FOR_CMD_LINE : Only part of command circuit is reset.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SOFTWARE_RESET_FOR_DAT_LINE : Only part of data circuit is reset,DMA circuit is also reset.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Reserved1 : Reserved1
bits : 3 - 10 (8 bit)
access : read-write

COMMAND_COMPLETE : This bit is set when get the end bit of the command response. Auto CMD12 and Auto CMD23 consist of two responses.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRANSFER_COMPLETE : This bit is set when a read / write transfer and a command with busy is completed.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLOCK_GAP_EVENT : If the Stop At Block Gap Request in the Block Gap Control register is set, this bit is set when both a read or write transaction is stopped at a block gap.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_INTERRUPT : This status is set if the SMIHC Controller detects the Host SDMA Buffer boundary during transfer.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFFER_WRITE_READY : This status is set if the Buffer Write Enable changes from 0 to 1. Refer to the Buffer Write Enable in the Present State register.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFFER_READ_READY : This status is set if the Buffer Read Enable changes from 0 to 1. Refer to the Buffer Read Enable in the Present State register
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_INSERTION : This status is set if the Card Inserted in the Present State register changes from 0 to 1.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_REMOVAL : This status is set if the Card Inserted in the Present State register changes from 1 to 0
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_INTERRUPT : interrupt signal from the SD card and the interrupt to the Host System.
bits : 8 - 16 (9 bit)
access : read-only

INT_A : This status is set if INT_A is enabled and INT_A pin is in low level.
bits : 9 - 18 (10 bit)
access : read-only

INT_B : This status is set if INT_B is enabled and INT_B pin is in low level.
bits : 10 - 20 (11 bit)
access : read-only

INT_C : This status is set if INT_C is enabled and INT_C pin is in low level.
bits : 11 - 22 (12 bit)
access : read-only

RE_TUNING_EVENT : This status is set if Re-Tuning Request in the Present State register changes from 0 to 1.
bits : 12 - 24 (13 bit)
access : read-only

BOOT_ACK_COMPLETE_INTERRUPT : This status is set if Re-Tuning Request in the Present State register changes from 0 to 1.
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOOT_DONE_INTERRUPT : boot acknowledge interrupt
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERROR_INTERRUPT : If any of the bits in the Error Interrupt Status register are set, then this bit is set.
bits : 15 - 30 (16 bit)
access : read-only

COMMAND_TIMEOUT_ERROR : This bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_CRC_ERROR : Command CRC Error is generated in two cases.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_END_BIT_ERROR : This bit is set when detecting that the end bit of a command response is 0.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_INDEX_ERROR : This bit is set if a Command Index error occurs in the command response.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_TIMEOUT_ERROR : This bit is set when detecting one of following timeout conditions ,Busy timeout for R1b,R5b type, busy timeout after write CRC status,write CRC Status timeout,read data timeout.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_CRC_ERROR : Occurs when detecting CRC error when transferring read data which uses the DAT line
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_END_BIT_ERROR : Occurs either when detecting 0 at the end bit position of read data which uses the DAT line or at the end bit position of the CRC Status.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CURRENT_LIMIT_ERROR : By setting the SD Bus Power bit in the Power Control register, the SMIHC Controller is requested to supply power for the SD Bus
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CMD_ERROR : Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMA_ERROR : This bit is set when the SMIHC Controller detects errors during ADMA based data transfer.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TUNING_ERROR : This bit is set when an unrecoverable error is detected in a tuning circuit.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Reserved1 : Reserved1
bits : 11 - 26 (16 bit)
access : read-write

COMMAND_COMPLETE_STATUS_ENABLE : Command Complete Status Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRANSFER_COMPLETE_STATUS_ENABLE : Command Complete Status Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLOCK_GAP_EVENT_STATUS_ENABLE : Command Complete Status Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_INTERRUPT_STATUS_ENABLE : DMA Interrupt Status Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFFER_WRITE_READY_STATUS_ENABLE : DMA Interrupt Status Enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFFER_READ_READY_STATUS_ENABLE : Buffer Read Ready Status Enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_INSERTION_STATUS_ENABLE : Card Insertion Status Enable
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_REMOVAL_STATUS_ENABLE : Card Insertion Status Enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_INTERRUPT_STATUS_ENABLE : If this bit is set to 0, the SMIHC Controller shall clear interrupt request to the System
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT_A_STATUS_ENABLE : The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.
bits : 9 - 18 (10 bit)
access : read-write

INT_B_STATUS_ENABLE : The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.
bits : 10 - 20 (11 bit)
access : read-write

INT_C_STATUS_ENABLE : The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts.
bits : 11 - 22 (12 bit)
access : read-write

RETUNING_EVENT_STATUS_ENABLE : Re-Tuning Event Status enable
bits : 12 - 24 (13 bit)
access : read-write

BOOT_ACK_COMPLETE_INTERRUPT_STATUS_ENABLE : If this bit is set to 0, the SMIHC Controller shall clear interrupt request to the System
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOOT_DONE_INTERRUPT_STATUS_ENABLE : Boot Done Interrupt Status Enable
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIXED_TO_0 : The Host Driver shall control error interrupts using the Error Interrupt Status Enable register.
bits : 15 - 30 (16 bit)
access : read-only

COMMAND_TIMEOUT_ERROR_STATUS_ENABLE : Command Timeout Error Status Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_CRC_ERROR_STATUS_ENABLE : Command Timeout Error Status Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_END_BIT_ERROR_STATUS_ENABLE : Command Timeout Error Status Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_INDEX_ERROR_STATUS_ENABLE : Command Index Error Status Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_TIMEOUT_ERROR_STATUS_ENABLE : Data Timeout Error Status Enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_CRC_ERROR_STATUS_ENABLE : Data Timeout Error Status Enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_END_BIT_ERROR_STATUS_ENABLE : Data End Bit Error Status Enable
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CURRENT_LIMIT_ERROR_STATUS_ENABLE : Data End Bit Error Status Enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CMD_ERROR_STATUS_ENABLE : Auto CMD Error Status Enable
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMA_ERROR_STATUS_ENABLE : Auto CMD Error Status Enable
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TUNING_ERROR_STATUS_ENABLE : Tuning Error Status Enable
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Reserved1 : Reserved1
bits : 11 - 22 (12 bit)
access : read-write

VENDOR_SPECIFIC_ERROR_STATUS_ENABLE : Vendor Specific Error Status Enable
bits : 12 - 27 (16 bit)
access : read-write

COMMAND_COMPLETE_SIGNAL_ENABLE : Command Complete Signal Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRANSFER_COMPLETE_SIGNAL_ENABLE : Command Complete Signal Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLCOK_GAP_EVENT_SIGNAL_ENABLE : Block Gap Event Signal Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_INTERRUPT_SIGNAL_ENABLE : DMA Interrupt Signal Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFFER_WRITE_READY_SIGNAL_ENABLE : Buffer Write Ready Signal Enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFFER_READ_READY_SIGNAL_ENABLE : Buffer Read Ready Signal Enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_INSERTION_SIGNAL__ENABLE : Card Insertion Signal Enable
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_REMOVAL_SIGNAL__ENABLE : Card Insertion Signal Enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CARD_INTERRUPT_SIGNAL_ENABLE : Card Interrupt Signal Enable
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT_A_SIGNAL_ENABLE : INT_A Signal Enable
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT_B_SIGNAL_ENABLE : INT_B Signal Enable
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT_C_SIGNAL_ENABLE : INT_C Signal Enable
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RE_TUNNING_EVENT_SIGNAL_ENABLE : Re-Tuning Event Signal Enable
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOOT_ACK_COMPLETE_INTERRUPT_SIGNAL_ENABLE : Boot Ack Complete Interrupt Signal Enable
bits : 13 - 26 (14 bit)
access : read-only

BOOT_DONE_INTERRUPT_SIGNAL_ENABLE : Boot Ack Complete Interrupt Signal Enable
bits : 14 - 28 (15 bit)
access : read-only

FIXED_TO_0 : The Host Driver shall control error interrupts using the Error Interrupt Signal Enable register.
bits : 15 - 30 (16 bit)
access : read-only

COMMAND_TIMEOUT_ERROR_SIGNAL_ENABLE : Command Timeout Error Signal Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_CRC_ERROR_SIGNAL_ENABLE : Command CRC Error Signal Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_END_BIT_ERROR_SIGNAL_ENABLE : Command End Bit Signal Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_INDEX_ERROR_SIGNAL_ENABLE : Command Index Signal Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_TIMEOUT_ERROR_SIGNAL_ENABLE : Data Timeout Error Signal Enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_CRC_ERROR_SIGNAL_ENABLE : Data CRC Error Signal Enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_END_BIT_ERROR_SIGNAL_ENABLE : Data CRC Error Signal Enable
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CURRENT_LIMIT_ERROR_SIGNAL_ENABLE : Data CRC Error Signal Enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CMD_ERROR_SIGNAL_ENABLE : Auto CMD Error Signal Enable
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMA_ERROR_SIGNAL_ENABLE : ADMA Error Signal Enable
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TUNING_ERROR_SIGNAL_ENABLE : Tuning Error Signal Enable
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 22 (12 bit)
access : read-write

VENDOR_SPECIFIC_ERROR_STATUS_ENABLE : Vendor Specific Error Status Enable
bits : 12 - 27 (16 bit)
access : read-write

AUTO_CMD12_NOT_EXECUTED : If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

AUTO_CMD_TIME_ERROR : This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command.
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

AUTO_CMD_CRC_ERROR : This bit is set when detecting a CRC error in the command response
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

AUTO_CMD_END_BIT_ERROR : This bit is set when detecting that the end bit of command response is 0.
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

AUTO_CMD_INDEX_ERROR : This bit is set if the Command Index error occurs in response to a command.
bits : 4 - 8 (5 bit)
access : read-only

RESERVED1 : reserved1
bits : 5 - 11 (7 bit)
access : read-only

COMMAND_NOT_ISSUED_BY_AUTO_CMD12_ERROR : Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register.
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED2 : reserved2
bits : 8 - 23 (16 bit)
access : read-only

UHS_MODE_SELECT : This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIGNALING_1_8V_ENABLE : This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DRIVER_STRENGTH_SELECT : SMIHC Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective.
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXECUTE_TUNNING : This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAMPLING_CLOCK_SELECT : SMIHC Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 04-05 bits of Drive Strength select.
bits : 8 - 16 (9 bit)
access : read-write

RESERVED1 : Reserved1
bits : 9 - 22 (14 bit)
access : read-write

ASYNCHRONOUS_INTERRUPT_ENABLE : This bit can be set to 1 if a card that supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRESET_VALUE_ENABLE : As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver.
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRANSFER_BLOCK_SIZE : This register specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to the maximum buffer size
bits : 0 - 11 (12 bit)
access : read-write

HOST_SDMA_BUFFER_BOUNDARY : Host Driver to update the SDMA System Address register. At the end of transfer, the SMIHC Controller may issue or may not issue DMA Interrupt.
bits : 12 - 26 (15 bit)
access : read-write

RESERVED1 : Reserved1
bits : 15 - 30 (16 bit)
access : read-write

TIMEOUT_CLOCK_FREQUENCY : This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock Unit defines the unit of this field's value.
bits : 0 - 5 (6 bit)
access : read-write

RESERVED1 : Reserved1
bits : 6 - 12 (7 bit)
access : read-write

TIMEOUT_CLOCK_UNIT : This bit shows the unit of base clock frequency used to detect Data Timeout Error.
bits : 7 - 20 (14 bit)
access : read-write

BASE_CLOCK_FREQUENCY : This value indicates the base (maximum) clock frequency for the SD Clock. Definition of this field depends on Host Controller Version.
bits : 14 - 35 (22 bit)
access : read-write

MAXIMUM_BLOCK_LENGTH : This value indicates the maximum block size that the Host Driver can read and write to the buffer in the SMIHC Controller.
bits : 22 - 45 (24 bit)
access : read-write

_8BIT_SUPPORT_FOR_EMDDED_DEVICE : This bit indicates whether the SMIHC Controller is capable of using 8-bit bus width mode. This bit is not effective when slot Type is set to 10b.
bits : 24 - 48 (25 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMA2_SUPPORT : This bit indicates whether the SMIHC Controller is capable of using ADMA2.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED2 : This bit is reserved for backward compatibility with prior specifications. If set, the SMIHC Controller is indicating that it supports legacy ADMA1 mode.
bits : 26 - 52 (27 bit)
access : read-write

HIGH_SPEED_SUPPORT : This bit indicates whether the SMIHC Controller and the Host System support High Speed mode and they can supply SD Clock frequency from 25MHz to 50MHz.
bits : 27 - 54 (28 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDMA_SUPPORT : This bit indicates whether the SMIHC Controller is capable of using SDMA to transfer data between system memory and the SMIHC Controller directly.
bits : 28 - 56 (29 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SUSPEND_RESUME_SUPPORT : This bit indicates whether the SMIHC Controller does not supports Suspend or Resume functionality.
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDR50_SUPPORT : SDR50 SUPPORT
bits : 30 - 60 (31 bit)
access : read-write

SDR104_SUPPORT : SDR104 SUPPORT
bits : 31 - 62 (32 bit)
access : read-write

DDR50_SUPPORT : DDR50 SUPPORT
bits : 32 - 64 (33 bit)
access : read-write

HS200_SUPPORT : HS200 SUPPORT
bits : 33 - 66 (34 bit)
access : read-write

DRIVER_TYPEA_SUPPORT : DRIVER_TYPEA SUPPORT
bits : 34 - 68 (35 bit)
access : read-write

DRIVER_TYPEC_SUPPORT : DRIVER_TYPEC SUPPORT
bits : 35 - 70 (36 bit)
access : read-write

DRIVER_TYPED_SUPPORT : DRIVER_TYPED SUPPORT
bits : 36 - 72 (37 bit)
access : read-write

HS400_SUPPORT : HS400 SUPPORT
bits : 37 - 74 (38 bit)
access : read-write

RESERVED3 : RESERVED3
bits : 38 - 79 (42 bit)
access : read-write

RESERVED4 : RESERVED4
bits : 42 - 84 (43 bit)
access : read-write

USE_TUNING_FOR_SDR50 : As this bit is set to 1, before using the SDR50 mode, the tuning procedure at the initialization sequence will be executed regardless of Re-Tuning Modes state in the Capabilities register.
bits : 43 - 86 (44 bit)
access : read-write

RE_TUNNING_MODES : This field selects re-tuning method and limits the maximum data length.
bits : 44 - 89 (46 bit)
access : read-write

CLOCK_MULTIPLIER : CLOCK MULTIPLIER
bits : 46 - 99 (54 bit)
access : read-write

RESERVED5 : Reserved5
bits : 54 - 117 (64 bit)
access : read-write

ADMA_ERROR_STATE : This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state.
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADMA_LENGHT_MISMATCH_ERROR : While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length.
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : Reserved1
bits : 3 - 34 (32 bit)
access : read-only

BLOCK_COUNT_FOR_CURRENT_TRANSFER : This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers.
bits : 0 - 15 (16 bit)
access : read-write

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDCLK_FREQUENCY_SELECT_VALUE : 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
bits : 0 - 9 (10 bit)
access : read-only

CLOCK_GENERATOR_SELECT_VALUE : This bit is effective when Host Controller supports programmable clock generator
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RESERVED1 : reserved1
bits : 11 - 23 (13 bit)
access : read-only

UPPER_BIT_OF_DRIVER_STRENGTH_SELECT : This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
bits : 13 - 26 (14 bit)
access : read-only

DRIVER_STRENGTH_SELECT_VALUE : Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
bits : 14 - 29 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

COMMAND_ARGUMENT_1 : The SD command argument is specified as bit 39-8 of Command-Format in the Physical Layer Specification.
bits : 0 - 31 (32 bit)
access : read-write

DMA_ENABLE : This bit enables DMA functionality. DMA can be enabled only if it is supported as indicated in the Capabilities register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLOCK_COUNT_ENABLE : This bit is used to enable the Block Count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled,
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CMD_ENABLE : This field determines use of auto command functions.
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_TRANSFER_DIRECTION_SELECT : This bit defines the direction of DAT line data transfers. The bit is set to 1 by the Host Driver to transfer data from the SD card to the SMIHC Controller and
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MULTI_OR_SINGLE_BLOCK_SELECT : This bit is set when issuing multiple-block transfer commands using DAT line.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : RESERVED1
bits : 6 - 15 (10 bit)
access : read-only

MMC_CMD23 : The Host driver has to set this bit for MMC CMD23
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STREAM_MODE_ENABLE : The Host driver has to set this bit for MMC CMD11 or CMD20 Stream Read/Write Operations.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI_MODE_ENABLE : Enable or disable SPI mode
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOOT_ACK_ENABLE : Enable or disable boot ack
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALTERNATE_BOOT_OPERATION : Host Driver should set this bit only for Alternate Boot Operation. For Normal Transaction, this bit should always be zero.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOOT_OPERATION : Host Driver should set this bit only for Boot Operation. For Normal Transaction, this bit should always be zero.
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESPONSE_TYPE_SELECT : This register explain the response type select.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED1 : RESERVED1
bits : 2 - 4 (3 bit)
access : read-write

COMMAND_CRC_CHECK_ENABLE : If this bit is set to 1, the SMIHC Controller shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_INDEX_CHECK_ENABLE : If this bit is set to 1, the SMIHC Controller shall check the Index field in the response to see if it has the same value as the command index.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_PRESENT_SELECT : This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_TYPE : There are three types of special commands like Suspend, Resume and Abort. These bits shall be set to 00b for all other commands.
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMMAND_INDEX : These bits shall be set to the command number (CMD0-63, ACMD0-63) that is specified in bits 45-40 of the Command-Format in the Physical Layer Specification
bits : 8 - 21 (14 bit)
access : read-write

RESERVED2 : RESERVED2
bits : 14 - 29 (16 bit)
access : read-write