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SERIAL_IO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection :

Registers

DLL

THR

RBR

MCR

LSR

MSR

SCR

TER

DLM

IE

RS485CTRL

RS485ADDR

RS485DLY

LCTL

FCR

IIR

LCR


DLL

Divisor LSB(DLAB=1)
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL DLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

THR

Transmit(DLAB=0)
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
alternate_register : DLL
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RBR

Receive(DLAB=0)
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
alternate_register : DLL
reset_Mask : 0x0

RBR RBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCR

UART Modem Control
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTR RTS OUT1 OUT2 LB Reserved0 CTSEN

DTR : !DTRn Pin
bits : 0 - 0 (1 bit)

Enumeration:

0 : High

DTRn=1

1 : Low

DTRn=0

End of enumeration elements list.

RTS : !RTSn Pin
bits : 1 - 2 (2 bit)

Enumeration:

0 : High

RTSn=1

1 : Low

RTSn=0

End of enumeration elements list.

OUT1 : !OUT1n Pin
bits : 2 - 4 (3 bit)

Enumeration:

0 : High

OUT1n=1

1 : Low

OUT1n=0

End of enumeration elements list.

OUT2 : !OUT2n Pin
bits : 3 - 6 (4 bit)

Enumeration:

0 : High

OUT2n=1

1 : Low

OUT2n=0

End of enumeration elements list.

LB : Loopback Test
bits : 4 - 8 (5 bit)

Enumeration:

0 : Normal

No Loopback

1 : Test

Loopback

End of enumeration elements list.

Reserved0 : Reserved-Keep Low
bits : 6 - 12 (7 bit)

Enumeration:

0 : Low

OK

1 : High

Correct to 0

End of enumeration elements list.

CTSEN : CTS Enable
bits : 7 - 14 (8 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


LSR

UART Line Status
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LSR LSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR OE PE FE BI TFE TFI RFE

RDR : RX FIFO Empty
bits : 0 - 0 (1 bit)

Enumeration:

0 : Empty

Empty RX FIFO

1 : Data

Data in RX FIFO

End of enumeration elements list.

OE : Overrun Error
bits : 1 - 2 (2 bit)

Enumeration:

0 : None

No Overrun

1 : Error

Overrun Error

End of enumeration elements list.

PE : Parity Error
bits : 2 - 4 (3 bit)

Enumeration:

0 : None

No Parity Error

1 : Error

Parity Error

End of enumeration elements list.

FE : Framing Error
bits : 3 - 6 (4 bit)

Enumeration:

0 : None

No Framing Error

1 : Error

Framing Error

End of enumeration elements list.

BI : Break Detection
bits : 4 - 8 (5 bit)

Enumeration:

0 : None

No Break

1 : Break

Break Detected

End of enumeration elements list.

TFE : TX FIFO Empty
bits : 5 - 10 (6 bit)

Enumeration:

0 : Data

TX FIFO has Data

1 : Empty

TX FIFO Empty

End of enumeration elements list.

TFI : TX Empty
bits : 6 - 12 (7 bit)

Enumeration:

0 : Data

TX has Data

1 : Empty

TX Empty

End of enumeration elements list.

RFE : Parity/Framing in FIFO
bits : 7 - 14 (8 bit)

Enumeration:

0 : OK

RX FIFO OK

1 : Error

RX FIFO Contains Errors

End of enumeration elements list.


MSR

UART Modem Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSR MSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCTS DDSR DRI DDCD CTS DSR RI DCD

DCTS : CTS Changed
bits : 0 - 0 (1 bit)

Enumeration:

0 : Unchanged

CTS Unchanged

1 : Changed

CTS Changed

End of enumeration elements list.

DDSR : DSR Changed
bits : 1 - 2 (2 bit)

Enumeration:

0 : Unchanged

DSR Unchanged

1 : Changed

DSR Changed

End of enumeration elements list.

DRI : RI Changed
bits : 2 - 4 (3 bit)

Enumeration:

0 : Unchanged

RI Unchanged

1 : Changed

RI Changed

End of enumeration elements list.

DDCD : DCD Changed
bits : 3 - 6 (4 bit)

Enumeration:

0 : Unchanged

DCD Unchanged

1 : Changed

DCD Changed

End of enumeration elements list.

CTS : CTS Value
bits : 4 - 8 (5 bit)

Enumeration:

0 : High

CTS High

1 : Low

CTS Low

End of enumeration elements list.

DSR : DSR Value
bits : 5 - 10 (6 bit)

Enumeration:

0 : High

DSR High

1 : Low

DSR Low

End of enumeration elements list.

RI : RI Value
bits : 6 - 12 (7 bit)

Enumeration:

0 : High

RI High

1 : Low

RI Low

End of enumeration elements list.

DCD : DCD Value
bits : 7 - 14 (8 bit)

Enumeration:

0 : High

DCD High

1 : Low

DCD Low

End of enumeration elements list.


SCR

UART Scratch
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TER

UART Transmit Enable
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TER TER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TER

TER : TX Enable
bits : 7 - 14 (8 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


DLM

Divisor MSB(DLAB=1)
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLM DLM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IE

Interrupt Enable(DLAB=0)
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : DLM
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBR THRE RLS MSR LSYNC LFC

RBR : RX Data Available
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

THRE : TX Empty
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RLS : RX Line Status
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

MSR : Modem Status
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

LSYNC : LIN Sync
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

LFC : LIN Frame Complete
bits : 5 - 10 (6 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


RS485CTRL

UART RS485 Control
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RS485CTRL RS485CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMMEN RXDIS AADEN SEL DCTRL OINV

NMMEN : Normal Multidrop Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RXDIS : RX Disable
bits : 1 - 2 (2 bit)

Enumeration:

0 : Enable

Enabled

1 : Disable

Disabled

End of enumeration elements list.

AADEN : Auto Address Detection
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

SEL : Control Pin Select
bits : 3 - 6 (4 bit)

Enumeration:

0 : RTSN

RTSN Selected

1 : DTSN

DTRN Selected

End of enumeration elements list.

DCTRL : Direction Control
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

OINV : Direction Control Polarity
bits : 5 - 10 (6 bit)

Enumeration:

0 : Low

Low Active

1 : High

High Active

End of enumeration elements list.


RS485ADDR

UART RS485 Address
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RS485ADDR RS485ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RS485DLY

UART RS485 Delay
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RS485DLY RS485DLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCTL

UART LIN Control
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCTL LCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable LIN
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


FCR

UART FIFO Control
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FCR FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFR TFR RXTL

RFR : Reset RX FIFO
bits : 1 - 2 (2 bit)

Enumeration:

0 : NA

No Action

1 : Reset

Reset RX FIFO

End of enumeration elements list.

TFR : Reset TX FIFO
bits : 2 - 4 (3 bit)

Enumeration:

0 : NA

No Action

1 : Reset

Reset TX FIFO

End of enumeration elements list.

RXTL : RX FIFO Trigger
bits : 6 - 13 (8 bit)

Enumeration:

0 : 1

One Byte

1 : 4

Four Bytes

2 : 8

Eight Bytes

3 : 14

Fourteen Bytes

End of enumeration elements list.


IIR

Interrupt
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
alternate_register : FCR
reset_Mask : 0x0

IIR IIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCR

UART Line Control
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR LCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLS SBS PES EPS SPS BCS DLAB DIV8

WLS : Word Length
bits : 0 - 1 (2 bit)

Enumeration:

0 : 5

Five Bits

1 : 6

Six Bits

2 : 7

Seven Bits

3 : 8

Eight Bits

End of enumeration elements list.

SBS : Stop Bits
bits : 2 - 4 (3 bit)

Enumeration:

0 : 1

1 Stop

1 : 1.5

1.5 Stop

End of enumeration elements list.

PES : Parity Enable
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

EPS : Even Parity Enable
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

SPS : Sticky Parity Enable
bits : 5 - 10 (6 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

BCS : Break Control
bits : 6 - 12 (7 bit)

Enumeration:

0 : Off

Disabled

1 : On

Enabled

End of enumeration elements list.

DLAB : Address Switch
bits : 7 - 14 (8 bit)

Enumeration:

0 : Std

Standard

1 : Alt

Alternate

End of enumeration elements list.

DIV8 : Sample Clock
bits : 8 - 16 (9 bit)

Enumeration:

0 : 16-Bit

16-Bit Sample

1 : 8-Bit

8-Bit Sample

End of enumeration elements list.



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