\n
address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
Interrupt Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : Match Interrupt Status and Clear
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR1 : Match Interrupt Status and Clear
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR2 : Match Interrupt Status and Clear
bits : 2 - 4 (3 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR3 : Match Interrupt Status and Clear
bits : 3 - 6 (4 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
CAP : Capture Interrupt Status and Clear
bits : 4 - 8 (5 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
Prescale Counter
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Match Control
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0I : Match 0 Interrupt Enable
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR0R : Match 0 Reset Enable
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR0S : Match 0 Stop Enable
bits : 2 - 4 (3 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR1I : Match 1 Interrupt Enable
bits : 3 - 6 (4 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR1R : Match 1 Reset Enable
bits : 4 - 8 (5 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR1S : Match 1 Stop Enable
bits : 5 - 10 (6 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR2I : Match 2 Interrupt Enable
bits : 6 - 12 (7 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR2R : Match 2 Reset Enable
bits : 7 - 14 (8 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR2S : Match 2 Stop Enable
bits : 8 - 16 (9 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR3I : Match 3 Interrupt Enable
bits : 9 - 18 (10 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR3R : Match 3 Reset Enable
bits : 10 - 20 (11 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
MR3S : Match 3 Stop Enable
bits : 11 - 22 (12 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
Match
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Match
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Match
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Match
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Capture Control
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RE : Rising Edge Capture
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
FE : Falline Edge Capture
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
I : Capture Interrupt Enable
bits : 2 - 4 (3 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
ROC : Reset Timer on Capture
bits : 4 - 8 (5 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
Capture Value
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
External Match Control
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : Match 0 Output State
bits : 0 - 0 (1 bit)
Enumeration:
0 : Low
Low Level
1 : High
High Level
End of enumeration elements list.
EM1 : Match 1 Output State
bits : 1 - 2 (2 bit)
Enumeration:
0 : Low
Low Level
1 : High
High Level
End of enumeration elements list.
EM2 : Match 2 Output State
bits : 2 - 4 (3 bit)
Enumeration:
0 : Low
Low Level
1 : High
High Level
End of enumeration elements list.
EM3 : Match 3 Output State
bits : 3 - 6 (4 bit)
Enumeration:
0 : Low
Low Level
1 : High
High Level
End of enumeration elements list.
EMC0 : Match 0 Output Action
bits : 4 - 9 (6 bit)
Enumeration:
0 : NA
No Action
1 : Clear
Clear on Match
2 : Set
Set on Match
3 : Toggle
Toggle on Match
End of enumeration elements list.
EMC1 : Match 1 Output Action
bits : 6 - 13 (8 bit)
Enumeration:
0 : NA
No Action
1 : Clear
Clear on Match
2 : Set
Set on Match
3 : Toggle
Toggle on Match
End of enumeration elements list.
EMC2 : Match 2 Output Action
bits : 8 - 17 (10 bit)
Enumeration:
0 : NA
No Action
1 : Clear
Clear on Match
2 : Set
Set on Match
3 : Toggle
Toggle on Match
End of enumeration elements list.
EMC3 : Match 3 Output Action
bits : 10 - 21 (12 bit)
Enumeration:
0 : NA
No Action
1 : Clear
Clear on Match
2 : Set
Set on Match
3 : Toggle
Toggle on Match
End of enumeration elements list.
Timer Control
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter Enable
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
CRST : Counter Reset
bits : 1 - 2 (2 bit)
Enumeration:
0 : NA
No Action
1 : Reset
Reset Counter
End of enumeration elements list.
Counter/Timer Control
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTM : Counter/Timer Mode
bits : 0 - 1 (2 bit)
Enumeration:
0 : System
System Clock Timer
1 : Rising
Capture on Rising Edge
2 : Falling
Capture on Falling Edge
3 : Both
Capture on Both Edges
End of enumeration elements list.
AUTO : Capture Pin or RxD Pin
bits : 2 - 4 (3 bit)
Enumeration:
0 : Capture
Capture Pin
1 : RxD
RxD Pin
End of enumeration elements list.
PWM Control
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN0 : Enable PWM on MAT0 Pin
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
EN1 : Enable PWM on MAT1 Pin
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
EN2 : Enable PWM on MAT2 Pin
bits : 2 - 4 (3 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
EN3 : Enable PWM on MAT3 Pin
bits : 3 - 6 (4 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
Match Output Control
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV0 : Invert MAT0 Pin
bits : 0 - 0 (1 bit)
Enumeration:
0 : NA
No Action
1 : Invert
Invert Pin
End of enumeration elements list.
INV1 : Invert MAT1 Pin
bits : 1 - 2 (2 bit)
Enumeration:
0 : NA
No Action
1 : Invert
Invert Pin
End of enumeration elements list.
INV2 : Invert MAT2 Pin
bits : 2 - 4 (3 bit)
Enumeration:
0 : NA
No Action
1 : Invert
Invert Pin
End of enumeration elements list.
INV3 : Invert MAT3 Pin
bits : 3 - 6 (4 bit)
Enumeration:
0 : NA
No Action
1 : Invert
Invert Pin
End of enumeration elements list.
X01 : Exclusive OR on MAT0/1 Pins
bits : 4 - 8 (5 bit)
Enumeration:
0 : NA
No Action
1 : XOR
Exclusive OR
End of enumeration elements list.
X23 : Exclusive OR on MAT2/3 Pins
bits : 5 - 10 (6 bit)
Enumeration:
0 : NA
No Action
1 : XOR
Exclusive OR
End of enumeration elements list.
Match Output
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAT0 : Match Occurred
bits : 0 - 0 (1 bit)
Enumeration:
0 : No
No Match
1 : Match
Match Occurred
End of enumeration elements list.
MAT1 : Match Occurred
bits : 1 - 2 (2 bit)
Enumeration:
0 : No
No Match
1 : Match
Match Occurred
End of enumeration elements list.
MAT2 : Match Occurred
bits : 2 - 4 (3 bit)
Enumeration:
0 : No
No Match
1 : Match
Match Occurred
End of enumeration elements list.
MAT3 : Match Occurred
bits : 3 - 6 (4 bit)
Enumeration:
0 : No
No Match
1 : Match
Match Occurred
End of enumeration elements list.
CAP : Capture Occurred
bits : 4 - 8 (5 bit)
Enumeration:
0 : No
No Capture
1 : Capture
Capture Occurred
End of enumeration elements list.
Timer Count
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Prescale Compare
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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