\n
address_offset : 0x0 Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection :
Interrupt Enable
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
Raw Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RIS : Interrupt Status
bits : 0 - 0 (1 bit)
Enumeration:
0 : None
No Interrupt
1 : Interrupt
Interrupted
End of enumeration elements list.
Masked Interrupt Status
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIS : Interrupt Status
bits : 0 - 0 (1 bit)
Enumeration:
0 : None
No Interrupt
1 : Interrupt
Interrupted
End of enumeration elements list.
Interrupt Clear
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
alternate_register : MIS
reset_Mask : 0x0
ICR : Interrupt Clear
bits : 0 - 0 (1 bit)
Enumeration:
0 : NA
No Action
1 : Clear
Clear Interrupt
End of enumeration elements list.
Test Mode
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTM : Test Mode
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
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