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CONFIG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :

Registers

CONFIG

MIS

ICR

ERR_CONFIG

MIN_A

MAX_A

MIN_B

MAX_B

MIN_C

MAX_C

MIN_D

MAX_D

BUS_CONFIG

IE

RIS


CONFIG

Configuration
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSA CSB CSC CSD PEVEN PSTICK X9 CEH

CSA : CS A Enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

CSB : CS B Enable
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

CSC : CS C Enable
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

CSD : CS D Enable
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

PEVEN : Even Parity
bits : 4 - 8 (5 bit)

Enumeration:

0 : Even

Even Parity

1 : Odd

Odd Parity

End of enumeration elements list.

PSTICK : Sticky Parity
bits : 5 - 10 (6 bit)

Enumeration:

0 : Non-stick

No Sticky Parity

1 : Stick

Sticky Parity

End of enumeration elements list.

X9 : 9-Bit Bus
bits : 6 - 12 (7 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

CEH : CS Cycle Deselect
bits : 7 - 14 (8 bit)

Enumeration:

0 : NA

No Action

1 : Insert

Deselect Inserted Between Transactions

End of enumeration elements list.


MIS

Masked External Interrupt
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR EINT

PAR : Masked Parity Interrupt
bits : 0 - 0 (1 bit)

Enumeration:

0 : None

No Interrupt

1 : Interrupt

Interrupted

End of enumeration elements list.

EINT : Masked External Interrupt
bits : 1 - 2 (2 bit)

Enumeration:

0 : None

No Interrupt

1 : Interrupt

Interrupted

End of enumeration elements list.


ICR

Interrupt Clear
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
alternate_register : MIS
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR EINT

PAR : Parity Interrupt Clear
bits : 0 - 0 (1 bit)

Enumeration:

0 : NA

No Action

1 : Clear

Clear Interrupt

End of enumeration elements list.

EINT : External Interrupt Clear
bits : 1 - 2 (2 bit)

Enumeration:

0 : NA

No Action

1 : Clear

Clear Interrupt

End of enumeration elements list.


ERR_CONFIG

Error Configuration
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERR_CONFIG ERR_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT Reserved0

TIMEOUT : Bus Timeout Enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

Reserved0 : Reserved Storage
bits : 1 - 3 (3 bit)

Enumeration:

0 : Zero

A Zero

1 : One

A One

2 : Two

A Two

3 : Three

A Three

End of enumeration elements list.


MIN_A

Minimum Addresses
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIN_A MIN_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAX_A

Maximum Addresses
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAX_A MAX_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MIN_B

Minimum Addresses
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIN_B MIN_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAX_B

Maximum Addresses
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAX_B MAX_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MIN_C

Minimum Addresses
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIN_C MIN_C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAX_C

Maximum Addresses
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAX_C MAX_C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MIN_D

Minimum Addresses
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIN_D MIN_D read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAX_D

Maximum Addresses
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAX_D MAX_D read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUS_CONFIG

Bus Configuration
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS_CONFIG BUS_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRE LAT FIXED

CRE : Config Register Enable Value
bits : 0 - 0 (1 bit)

Enumeration:

0 : Low

Low Level

1 : High

High Level

End of enumeration elements list.

LAT : Fixed Latency Length
bits : 1 - 4 (4 bit)

Enumeration:

: LatCnt

Latency Cycles

End of enumeration elements list.

FIXED : Fixed Latency Enable
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


IE

Interrupt Enable
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR EINT

PAR : Parity Interrupt Enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

EINT : External Interrupt Enable
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


RIS

Raw Interrupt Status
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR EINT

PAR : Raw Parity Interrupt
bits : 0 - 0 (1 bit)

Enumeration:

0 : None

No Interrupt

1 : Interrupt

Interrupted

End of enumeration elements list.

EINT : Raw External Interrupt
bits : 1 - 2 (2 bit)

Enumeration:

0 : None

No Interrupt

1 : Interrupt

Interrupted

End of enumeration elements list.



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