\n

SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD00 byte (0x0)
mem_usage : registers
protection :

Registers

SYSINT_STATUS

SYSRAM_STATUS

CHIP_ID0

CHIP_ID1

CHIP_ID2

CHIP_ID3

ETIMER_CFG

SYSTICK_CFG

SYSRAM_CTRL

ACCESS_EN

MISC_CTRL


SYSINT_STATUS

SYSINT status Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYSINT_STATUS SYSINT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPU_INTR EFLASH_INTR SYSRAM0_INTR SYSRAM0 SYSRAM1_INTR SYSRAM1

PPU_INTR : ppu_intr
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EFLASH_INTR : eflash_intr
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYSRAM0_INTR : sysram0_intr
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYSRAM0 : sysram0
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYSRAM1_INTR : sysram1_intr
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYSRAM1 : sysram1
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


SYSRAM_STATUS

SYSRAM status Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYSRAM_STATUS SYSRAM_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSRAM0_PARITY_ERR_ADDR SYSRAM1_PARITY_ERR_ADDR

SYSRAM0_PARITY_ERR_ADDR : sysram0_parity_err_addr
bits : 0 - 10 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYSRAM1_PARITY_ERR_ADDR : sysram1_parity_err_addr
bits : 16 - 26 (11 bit)
access : read-only

Enumeration:

End of enumeration elements list.


CHIP_ID0

CHIP_ID0 Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID0 CHIP_ID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHIP_ID1

CHIP_ID1 Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID1 CHIP_ID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHIP_ID2

CHIP_ID2 Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID2 CHIP_ID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHIP_ID3

CHIP_ID3 Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID3 CHIP_ID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETIMER_CFG

ETIMER confige Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETIMER_CFG ETIMER_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1_BKIN_FSEL TIM1_BKIN3 TIM3_BKIN_FSEL TIM3_BKIN3 TIM15_BKIN_FSEL TIM15_BKIN3 TIM16_BKIN_FSEL TIM16_BKIN3 TIM17_BKIN_FSEL TIM17_BKIN3

TIM1_BKIN_FSEL : Tim1_bkin_fsel
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM1_BKIN3 : Tim1_bkin3
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM3_BKIN_FSEL : Tim3_bkin_fsel
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM3_BKIN3 : Tim3_bkin3
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM15_BKIN_FSEL : Tim15_bkin_fsel
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM15_BKIN3 : Tim15_bkin3
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM16_BKIN_FSEL : Tim16_bkin_fsel
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM16_BKIN3 : Tim16_bkin3
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM17_BKIN_FSEL : Tim17_bkin_fsel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM17_BKIN3 : Tim17_bkin3
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYSTICK_CFG

SYSTICK confige Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSTICK_CFG SYSTICK_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCALIB SKEW NOREF

STCALIB : stcalib
bits : 0 - 23 (24 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SKEW : skew
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NOREF : noref
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYSRAM_CTRL

RAM control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSRAM_CTRL SYSRAM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSRAM0_PARITY_INTREN SYSRAM0_PARITY_ERR_CLR SYSRAM1_PARITY_INTREN SYSRAM1_PARITY_ERR_CLR

SYSRAM0_PARITY_INTREN : sysram0_parity_intren
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRAM0_PARITY_ERR_CLR : sysram0_parity_err_clr
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRAM1_PARITY_INTREN : sysram1_parity_intren
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRAM1_PARITY_ERR_CLR : sysram1_parity_err_clr
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


ACCESS_EN

ACCESS ENABLE Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACCESS_EN ACCESS_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MISC_CTRL

MISC control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CTRL MISC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART3MODE

UART3MODE : UART3MODE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.



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