\n
address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :
uart data buff
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : UART0 Send And Recive Data
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
FRAMING_ERROR : DMA Transmit Size
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PARITY_ERROR : DMA Transmit Size
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BREAK_ERROR : DMA Transmit Size
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
OVERRUN_ERROR : DMA Transmit Size
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART0 Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTS : Clear to Send
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
BUSY : Indicate Is Busy
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RXFE : Receive FIFO Empty
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
TXFF : Transmit FIFO Full
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RXFF : Receive FIFO Full
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
TXFE : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
uart board rate 0..15 is usefull
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
uart board rate mod 0..5 is usefull
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Line Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Send Break
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PEN : Parity Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
EPS : Even Parity Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
STP2 : 2 Stop Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
FEN : FIFO Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
WLEN : Word Length
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPS : Stick Parity Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART0 Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTEN : UART Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SIREN : SIR ENDEC Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SIRLP : SIR low-power IrDA mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
LBE : Loopback Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
TXE : Transmit Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RXE : Receive Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DTR : Data Transmit Ready
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RTS : Request to Send
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
OUT1 : Out1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
OUT2 : Out2
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RTSEN : Ready to Send hardware flow control enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CTSEN : Clear to Send hardware flow control enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
fifo int level select
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXIFLSEL : Transmit Interrupt FIFO Level Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RXIFLSEL : Receive Interrupt FIFO Level Select
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
int enable bit
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIMIM : nUARTRI Modem Interrupt mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CTSMIM : nUARTCTS Modem Interrupt mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DCDMIM : nUARTDCD Modem Interrupt mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DSRMIM : nUARTDSR Modem Interrupt mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RXIM : Receive Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
TXIM : Transmit Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RTIM : Receive Ttimeout Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
FEIM : Framing Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PEIM : Parity Error Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BEIM : Break Error Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
OEIM : Overrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART0 Int Rigio
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUARTRI_I : nUARTRI Modem Interrupt
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
NUARTCTS_I : nUARTCTS Modem Interrupt
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
NUARTDCD_I : nUARTDCD Modem Interrupt
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
NUARTDSR_I : nUARTDSR Modem Interrupt
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RECEIVE_I : Receive Interrupt
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
TRANSMIT_I : Transmit Interrupt
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RT_I : Receive Ttimeout Interrupt
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
FE_I : Framing Error Interrupt
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
PF_I : Parity Error Interrupt
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
BE_I : Break Error Interrupt
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
OE_I : Overrun Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
uart rx status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMING_ERROR : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PARITY_ERROR : DMA Transmit Size
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BREAK_ERROR : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
OVERRUN_ERROR : DMA Transmit Size
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART0 MASK Interrupt
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUARTRI_MI : nUARTRI Modem Masked Interrupt
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
NUARTCTS_MI : nUARTCTS Modem Masked Interrupt
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
NUARTDCD_MI : nUARTDCD Modem Masked Interrupt
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
NUARTDSR_MI : nUARTDSR Modem Masked Interrupt
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RECEIVE_MI : Receive Masked Interrupt
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
TRANSMIT_MI : Transmit Masked Interrupt
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RT_MI : Receive Ttimeout Masked Interrupt
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
FE_MI : Framing Error Masked Interrupt
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
PF_MI : Parity Error Masked Interrupt
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
BE_MI : Break Error Masked Interrupt
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
OE_MI : Overrun Error Masked Interrupt
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
UART0 Int Clear Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
C_NUARTRI_IM : Clear nUARTRI Modem Interrupt mask
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_NUARTCTS_IM : Clear nUARTCTS Modem Interrupt mask
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_NUARTDCD_IM : Clear nUARTDCD Modem Interrupt mask
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_NUARTDSR_IM : Clear nUARTDSR Modem Interrupt mask
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_RECEIVE_IM : Clear Receive Interrupt Mask
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_TRANSMIT_IM : Clear Transmit Interrupt Mask
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_RT_IM : Clear Receive Ttimeout Interrupt Mask
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_FE_IM : Clear Framing Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_PF_IM : Clear Parity Error Interrupt Mask
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_BE_IM : Clear Break Error Interrupt Mask
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
C_OE_IM : Clear Overrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
UART0 DMA Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFIFO_EN : nUARTRI Modem Interrupt mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
TXFIFO_EN : nUARTCTS Modem Interrupt mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMA_ERROR : nUARTDCD Modem Interrupt mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
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