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CHIPCTL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC04 byte (0x0)
mem_usage : registers
protection :

Registers

CLKCTRL

CLKEN_H01

INTMASK

STATUS0

STATUS1

CLKEN_H23

CLKEN_P01

CLKEN_P23

SRST_REQ_H01

SRST_REQ_H23

SRST_REQ_P01

SRST_REQ_P23

POWER_CTRL

OSC32K_CTRL

WAKEUP_CTRL

REMAP_CTRL

CLKCFG0

IWDT_CTRL

IWDT_CFG

IWDT_CLKDIV

IWDT_RLD

IWDT_STATUS

CLKCFG1

WT_CTRL

CHIP_KEY

WT_ALERM

WT_CNT

CLKCFG2

VERSION


CLKCTRL

CLKCTRL Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCTRL CLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCEN OSCDEN OSCSTOP OSCGAIN OSCREN OSCOIEN OSCSTS OSCSTB RCHEN RCHSTB RCHTRIM RCHPT PLLEN PLLLOCK

OSCEN : OSCEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCDEN : OSCDEN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCSTOP : OSCSTOP
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OSCGAIN : OSCGAIN
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCREN : OSCREN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCOIEN : OSCOIEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCSTS : OSCSTS
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCSTB : OSCSTB
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RCHEN : RCHEN
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCHSTB : RCHSTB
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RCHTRIM : RCHTRIM
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCHPT : RCHPT
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLEN : PLLEN
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLLOCK : PLLLOCK
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


CLKEN_H01

CLKEN_H01 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_H01 CLKEN_H01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_CLKEN PB_CLKEN PC_CLKEN PF_CLKEN

PA_CLKEN : PA_CLKEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB_CLKEN : PB_CLKEN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC_CLKEN : PC_CLKEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF_CLKEN : PF_CLKEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


INTMASK

INTMASK Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTMASK INTMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR_MASK POC_MASK CVM_MASK LVR_MASK LVD_MASK NRST_MASK WDTRST_MASK IWDTRST_MASK SRST_MASK LOCKUP_MASK SYSCLKMUX_RST_MASK IO_WAKEUP_MASK DEBUG_VALID_MASK RCH_MISS_MASK OSC_MISS_MASK PLL_MISS_MASK SYSCLKMUX_ERR_MASK SCLKSEL_CFGERR_MASK PLLSRC_CFGERR_MASK RCHEN_CFGERR_MASK OSCEN_CFGERR_MASK PLLEN_CFGERR_MASK

POR_MASK : POR_MASK
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POC_MASK : POC_MASK
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CVM_MASK : CVM_MASK
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVR_MASK : LVR_MASK
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVD_MASK : LVD_MASK
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NRST_MASK : NRST_MASK
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRST_MASK : WDTRST_MASK
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IWDTRST_MASK : IWDTRST_MASK
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRST_MASK : SRST_MASK
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOCKUP_MASK : LOCKUP_MASK
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLKMUX_RST_MASK : SYSCLKMUX_RST_MASK
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IO_WAKEUP_MASK : IO_WAKEUP_MASK
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DEBUG_VALID_MASK : DEBUG_VALID_MASK
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCH_MISS_MASK : RCH_MISS_MASK
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSC_MISS_MASK : OSC_MISS_MASK
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL_MISS_MASK : PLL_MISS_MASK
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLKMUX_ERR_MASK : SYSCLKMUX_ERR_MASK
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCLKSEL_CFGERR_MASK : SCLKSEL_CFGERR_MASK
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLSRC_CFGERR_MASK : PLLSRC_CFGERR_MASK
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCHEN_CFGERR_MASK : RCHEN_CFGERR_MASK
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCEN_CFGERR_MASK : OSCEN_CFGERR_MASK
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLEN_CFGERR_MASK : PLLEN_CFGERR_MASK
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


STATUS0

STATUS0 Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS0 STATUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR_EVENT POC_EVENT CVM_EVENT LVR_EVENT LVD_EVENT NRST_EVENT WDTRST_EVENT IWDTRST_EVENT SRST_EVENT LOCKUP_EVENT SYSCLKMUX_RST_EVENT IO_WAKEUP_EVENT DEBUG_VALID_EVENT RCH_MISS_EVENT OSC_MISS_EVENT PLL_MISS_MASK SYSCLKMUX_ERR_EVENT SCLKSEL_CFGERR_EVENT PLLSRC_CFGERR_EVENT RCHEN_CFGERR_EVENT OSCEN_CFGERR_EVENT PLLEN_CFGERR_EVENT

POR_EVENT : POR_EVENT
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POC_EVENT : POC_EVENT
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CVM_EVENT : CVM_EVENT
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVR_EVENT : LVR_EVENT
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVD_EVENT : LVD_EVENT
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NRST_EVENT : NRST_EVENT
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRST_EVENT : WDTRST_EVENT
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IWDTRST_EVENT : IWDTRST_EVENT
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRST_EVENT : SRST_EVENT
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOCKUP_EVENT : LOCKUP_EVENT
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLKMUX_RST_EVENT : SYSCLKMUX_RST_EVENT
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IO_WAKEUP_EVENT : IO_WAKEUP_EVENT
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DEBUG_VALID_EVENT : DEBUG_VALID_EVENT
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCH_MISS_EVENT : RCH_MISS_MEVENT
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSC_MISS_EVENT : OSC_MISS_EVENT
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL_MISS_MASK : PLL_MISS_MASK
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLKMUX_ERR_EVENT : SYSCLKMUX_ERR_EVENT
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCLKSEL_CFGERR_EVENT : SCLKSEL_CFGERR_EVENT
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLSRC_CFGERR_EVENT : PLLSRC_CFGERR_EVENT
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCHEN_CFGERR_EVENT : RCHEN_CFGERR_EVENT
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCEN_CFGERR_EVENT : OSCEN_CFGERR_EVENT
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLEN_CFGERR_EVENT : PLLEN_CFGERR_EVENT
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


STATUS1

STATUS1 Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS1 STATUS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCSTOP RCHSTB PLL_LOCK LVDFLAG CVMFLAG BGRFLAG IWDT_INTR

OSCSTOP : OSCSTOP
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RCHSTB : RCHSTB
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLL_LOCK : PLL_LOCK
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LVDFLAG : LVDFLAG
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CVMFLAG : CVMFLAG
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BGRFLAG : BGRFLAG
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

IWDT_INTR : IWDT_INTR
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


CLKEN_H23

CLKEN_H23 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_H23 CLKEN_H23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_CLKEN

CRC_CLKEN : CRC_CLKEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CLKEN_P01

CLKEN_P01 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_P01 CLKEN_P01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPU_CLKEN ERU_CLKEN DMA_CLKEN UART1_CLKEN UART2_CLKEN UART3_CLKEN UART4_CLKEN UART5_CLKEN UART6_CLKEN I2C_CLKEN SSP_CLKEN

PPU_CLKEN : PPU_CLKEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERU_CLKEN : ERU_CLKEN
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_CLKEN : DMA_CLKEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_CLKEN : UART1_CLKEN
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2_CLKEN : UART2_CLKEN
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART3_CLKEN : UART3_CLKEN
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART4_CLKEN : UART4_CLKEN
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART5_CLKEN : UART5_CLKEN
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART6_CLKEN : UART6_CLKEN
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C_CLKEN : I2C_CLKEN
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSP_CLKEN : SSP_CLKEN
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CLKEN_P23

CLKEN_P23 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_P23 CLKEN_P23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM14_CLKEN TIM15_CLKEN TIM16_CLKEN TIM17_CLKEN ADC_CLKEN ACMP_OPA_CLKEN TIM1_CLKEN TIM3_CLKEN

TIM14_CLKEN : TIM14_CLKEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM15_CLKEN : TIM15_CLKEN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM16_CLKEN : TIM16_CLKEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM17_CLKEN : TIM17_CLKEN
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_CLKEN : ADC_CLKEN
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_OPA_CLKEN : ACMP_OPA_CLKEN
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM1_CLKEN : TIM1_CLKEN
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM3_CLKEN : TIM3_CLKEN
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SRST_REQ_H01

SRST_REQ_H01 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_H01 SRST_REQ_H01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_SRST_REQ PB_SRST_REQ PC_SRST_REQ PF_SRST_REQ

PA_SRST_REQ : PA_SRST_REQ
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB_SRST_REQ : PB_SRST_REQ
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC_SRST_REQ : PC_SRST_REQ
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF_SRST_REQ : PF_SRST_REQ
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SRST_REQ_H23

SRST_REQ_H23 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_H23 SRST_REQ_H23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_SRST_REQ

CRC_SRST_REQ : CRC_SRST_REQ
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SRST_REQ_P01

SRST_REQ_P01 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_P01 SRST_REQ_P01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPU_SRST_REQ ERU_SRST_REQ DMA_SRST_REQ UART1_SRST_REQ UART2_SRST_REQ UART3_SRST_REQ UART4_SRST_REQ UART5_SRST_REQ UART6_SRST_REQ I2C_SRST_REQ SSP_SRST_REQ

PPU_SRST_REQ : PPU_SRST_REQ
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERU_SRST_REQ : ERU_SRST_REQ
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_SRST_REQ : DMA_SRST_REQ
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_SRST_REQ : UART1_SRST_REQ
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2_SRST_REQ : UART2_SRST_REQ
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART3_SRST_REQ : UART3_SRST_REQ
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART4_SRST_REQ : UART4_SRST_REQ
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART5_SRST_REQ : UART5_SRST_REQ
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART6_SRST_REQ : UART6_SRST_REQ
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C_SRST_REQ : I2C_SRST_REQ
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSP_SRST_REQ : SSP_SRST_REQ
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SRST_REQ_P23

SRST_REQ_P23 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_P23 SRST_REQ_P23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM14_SRST_REQ TIM15_SRST_REQ TIM16_SRST_REQ TIM17_SRST_REQ ADC_SRST_REQ ACMP_OPA_SRST_REQ TIM1_SRST_REQ TIM3_SRST_REQ

TIM14_SRST_REQ : TIM14_SRST_REQ
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM15_SRST_REQ : TIM15_SRST_REQ
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM16_SRST_REQ : TIM16_SRST_REQ
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM17_SRST_REQ : TIM17_SRST_REQ
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_SRST_REQ : ADC_SRST_REQ
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_OPA_SRST_REQ : ACMP_OPA_SRST_REQ
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM1_SRST_REQ : TIM1_SRST_REQ
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM3_SRST_REQ : TIM3_SRST_REQ
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


POWER_CTRL

POWER_CTRL Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER_CTRL POWER_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPE SYSCLK_MUX_RSTEN SYSCLK_DCTEN DEBUG_NOSLEEP FLASH_CG FLASH_LP SRAM_CG POCREN CVMREN LOCKUPREN MVRPS MVRSEL LVREN LVRS CVMEN LVDEN LVES LVLS VTSEN VTSEL

LPE : LPE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLK_MUX_RSTEN : SYSCLK_MUX_RSTEN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLK_DCTEN : SYSCLK_DCTEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DEBUG_NOSLEEP : DEBUG_NOSLEEP
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLASH_CG : FLASH_CG
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLASH_LP : FLASH_LP
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRAM_CG : SRAM_CG
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POCREN : POCREN
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CVMREN : CVMREN
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOCKUPREN : LOCKUPREN
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MVRPS : MVRPS
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MVRSEL : MVRSEL
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : LVREN
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRS : LVRS
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CVMEN : CVMEN
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDEN : LVDEN
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVES : LVES
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVLS : LVLS
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTSEN : VTSEN
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTSEL : VTSEL
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.


OSC32K_CTRL

OSC32K_CTRL Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC32K_CTRL OSC32K_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN REFEN DETEN FILEN INVEN FAST GAIN OSCDET

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFEN : REFEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DETEN : DETEN
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FILEN : FILEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INVEN : INVEN
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FAST : FAST
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GAIN : GAIN
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCDET : OSCDET
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


WAKEUP_CTRL

WAKEUP_CTRL Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKEUP_CTRL WAKEUP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO_WAKEUPEN IWDT_WAKEUPEN DEBUG_WAKEUPEN LVD_WAKEUPEN WT_WAKEUPEN

IO_WAKEUPEN : IO_WAKEUPEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IWDT_WAKEUPEN : IWDT_WAKEUPEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DEBUG_WAKEUPEN : DEBUG_WAKEUPEN
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVD_WAKEUPEN : LVD_WAKEUPEN
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WT_WAKEUPEN : WT_WAKEUPEN
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


REMAP_CTRL

REMAP_CTRL Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REMAP_CTRL REMAP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REMAP XRST_USEASFUNC SYSRESET_OUTEN SYSRESET_OUTSEL DEBUG_USEASFUNC REMAP_KEY

REMAP : REMAP
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XRST_USEASFUNC : XRST_USEASFUNC
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRESET_OUTEN : SYSRESET_OUTEN
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRESET_OUTSEL : SYSRESET_OUTSEL
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DEBUG_USEASFUNC : DEBUG_USEASFUNC
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REMAP_KEY : REMAP_KEY
bits : 16 - 31 (16 bit)
access : write-only

Enumeration:

End of enumeration elements list.


CLKCFG0

CLKCFG0 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCFG0 CLKCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSRC PLLDIV PLLMUL XCLKINSEL XCLKSEL XCLKDIV

PLLSRC : PLLSRC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLDIV : PLLDIV
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLMUL : PLLMUL
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKINSEL : XCLKINSEL
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKSEL : XCLKSEL
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKDIV : XCLKDIV
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.


IWDT_CTRL

IWDT_CTRL Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IWDT_CTRL IWDT_CTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONTROL

CONTROL : CONTROL
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

End of enumeration elements list.


IWDT_CFG

IWDT_CFG Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDT_CFG IWDT_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINEN WINSEL

WINEN : WINEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WINSEL : WINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


IWDT_CLKDIV

IWDT_CLKDIV Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDT_CLKDIV IWDT_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV

CLKDIV : CLKDIV
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


IWDT_RLD

IWDT_RLD Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDT_RLD IWDT_RLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLD

RLD : RLD
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.


IWDT_STATUS

IWDT_STATUS Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IWDT_STATUS IWDT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT INTR UPDATING

CNT : CNT
bits : 0 - 15 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INTR : INTR
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

UPDATING : UPDATING
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


CLKCFG1

CLKCFG1 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCFG1 CLKCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCLKSEL CLK32KSEL SYSCLKLOCK SYSTICKSEL IWRCLKSEL LEDCLKSEL

SYSCLKSEL : SYSCLKSEL
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK32KSEL : CLK32KSEL
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLKLOCK : SYSCLKLOCK
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYSTICKSEL : SYSTICKSEL
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IWRCLKSEL : IWRCLKSEL
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEDCLKSEL : LEDCLKSEL
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


WT_CTRL

WT_CTRL Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WT_CTRL WT_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WT_EN BUZ_SEL BK_SEL INTEN INT

WT_EN : WT_EN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUZ_SEL : BUZ_SEL
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK_SEL : BK_SEL
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : INTEN
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT : INT
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CHIP_KEY

CHIP_KEY Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_KEY CHIP_KEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


WT_ALERM

WT_ALERM Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WT_ALERM WT_ALERM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALERM

ALERM : ALERM
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.


WT_CNT

WT_CNT Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WT_CNT WT_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WT_CNT

WT_CNT : WT_CNT
bits : 0 - 22 (23 bit)
access : read-only

Enumeration:

End of enumeration elements list.


CLKCFG2

CLKCFG2 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCFG2 CLKCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDIV MTDIV PDIV01 PDIV23

HDIV : HDIV
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MTDIV : MTDIV
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDIV01 : PDIV01
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDIV23 : PDIV23
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


VERSION

VERSION Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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