\n
address_offset : 0x0 Bytes (0x0)
size : 0xC04 byte (0x0)
mem_usage : registers
protection :
WDT Reload Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT Original Interrput
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDOGINT : WDT Original Interrput flag Bit
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
WDT Mask Interrput
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDOGMINT : WDT Mask Interrput flag Bit
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
WDT Current Counter
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDT Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Interrput Enable Control Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RSTEN : RST Enable Control Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
WDT Interrput Clear
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WDT Locked Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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