Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSS : Data Size Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
FRF : Frame format
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPO : SSPCLKOUT polarity
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPH : SSPCLKOUT phase
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SCR : Serial Clock rate
bits : 8 - 15 (8 bit)
access : read-write
Clock prescale Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPSDVSR : Clock prescale divisor
bits : 0 - 7 (8 bit)
access : read-write
Interrupt Set or Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORIM : Receive overrun interrupt mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RTIM : Receive timeout interrupt mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RXIM : Receive FIFO interrupt mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
TXIM : Receive FIFO interrupt mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Raw Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORRIS : Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RTRIS : Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RXRIS : Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
TXRIS : Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Masked Interrupt Staus Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORMIS : Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RTMIS : Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RXMIS : Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
TXMIS : Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RORIC : Clears the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
RTIC : Clears the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
DMA Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDMAE : Receive DMA Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
TXDMAE : Transmit DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBM : Loop back mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SSE : Synchronous serial port enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
MS : Master or Slave mode select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SOD : Clear Data Overrun
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMALEV : DMA RX FIFO trig level
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit/Receive FIFO
bits : 0 - 15 (16 bit)
access : read-write
Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFE : Transmit FIFO emptyt
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
TNF : Transmit FIFO full
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RNE : Receive FIFO not empty
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
RFF : Receive FIFO full
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
BSY : PrimeCell SSP busy flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Peripheral Identification Register0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification Register1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification Register2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification Register3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PrimCell Identification Register0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PrimCell Identification Register1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PrimCell Identification Register2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PrimCell Identification Register3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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