\n

UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :

Registers

UARTDR

UARTFR

UARTIBRD

UARTFBRD

UARTLCR_H

UARTCR

UARTIFLS

UARTIMSC

UARTRIS

UARTRSR

UARTMIS

UARTICR

UARTDMACR


UARTDR

uart data buff
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTDR UARTDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA Framing_Error Parity_Error Break_Error Overrun_Error

DATA : UART0 Send And Recive Data
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Framing_Error : DMA Transmit Size
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Parity_Error : DMA Transmit Size
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Break_Error : DMA Transmit Size
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Overrun_Error : DMA Transmit Size
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


UARTFR

UART0 Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UARTFR UARTFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTS DSR DCD BUSY RXFE TXFF RXFF TXFE RI

CTS : Clear to Send
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DSR : Data Set Ready
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DCD : Data Carrier Detect
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUSY : Indicate Is Busy
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFE : Receive FIFO Empty
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFF : Transmit FIFO Full
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFF : Receive FIFO Full
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFE : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RI : Ring indicator
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


UARTIBRD

uart board rate 0..15 is usefull
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTIBRD UARTIBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UARTFBRD

uart board rate mod 0..5 is usefull
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTFBRD UARTFBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UARTLCR_H

Line Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTLCR_H UARTLCR_H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SB PE EPS STP2 FEN WLEN SPS

SB : Send Break
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PE : Parity Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPS : Even Parity Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STP2 : 2 Stop Bits
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEN : FIFO Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLEN : Word Length
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPS : Stick Parity Select
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


UARTCR

UART0 Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTCR UARTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UARTEN SIREN SIRLP LBE TXE RXE DTS RTS Out1 Out2 RTSEn CTSEn

UARTEN : UART Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIREN : SIR ENDEC Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIRLP : SIR low-power IrDA mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LBE : Loopback Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXE : Transmit Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXE : Receive Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTS : Data Transmit Ready
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS : Request to Send
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Out1 : Out1
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Out2 : Out2
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSEn : Ready to Send hardware flow control enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTSEn : Clear to Send hardware flow control enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


UARTIFLS

fifo int level select
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTIFLS UARTIFLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXIFLSEL RXIFLSEL

TXIFLSEL : Transmit Interrupt FIFO Level Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXIFLSEL : Receive Interrupt FIFO Level Select
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.


UARTIMSC

int enable bit
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTIMSC UARTIMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nUARTRI_IM nUARTCTS_IM nUARTDCD_IM nUARTDSR_IM Receive_IM Transmit_IM RT_IM FE_IM PF_IM BE_IM OE_IM

nUARTRI_IM : nUARTRI Modem Interrupt mask
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

nUARTCTS_IM : nUARTCTS Modem Interrupt mask
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

nUARTDCD_IM : nUARTDCD Modem Interrupt mask
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

nUARTDSR_IM : nUARTDSR Modem Interrupt mask
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Receive_IM : Receive Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Transmit_IM : Transmit Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RT_IM : Receive Ttimeout Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FE_IM : Framing Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF_IM : Parity Error Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BE_IM : Break Error Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OE_IM : Overrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


UARTRIS

UART0 Int Rigio
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UARTRIS UARTRIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nUARTRI_I nUARTCTS_I nUARTDCD_I nUARTDSR_I Receive_I Transmit_I RT_I FE_I PF_I BE_I OE_I

nUARTRI_I : nUARTRI Modem Interrupt
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

nUARTCTS_I : nUARTCTS Modem Interrupt
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

nUARTDCD_I : nUARTDCD Modem Interrupt
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

nUARTDSR_I : nUARTDSR Modem Interrupt
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

Receive_I : Receive Interrupt
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

Transmit_I : Transmit Interrupt
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RT_I : Receive Ttimeout Interrupt
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FE_I : Framing Error Interrupt
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PF_I : Parity Error Interrupt
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BE_I : Break Error Interrupt
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OE_I : Overrun Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


UARTRSR

uart rx status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTRSR UARTRSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Framing_Error Parity_Error Break_Error Overrun_Error

Framing_Error : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Parity_Error : DMA Transmit Size
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Break_Error : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Overrun_Error : DMA Transmit Size
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


UARTMIS

UART0 MASK Interrupt
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UARTMIS UARTMIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nUARTRI_MI nUARTCTS_MI nUARTDCD_MI nUARTDSR_MI Receive_MI Transmit_MI RT_MI FE_MI PF_MI BE_MI OE_MI

nUARTRI_MI : nUARTRI Modem Masked Interrupt
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

nUARTCTS_MI : nUARTCTS Modem Masked Interrupt
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

nUARTDCD_MI : nUARTDCD Modem Masked Interrupt
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

nUARTDSR_MI : nUARTDSR Modem Masked Interrupt
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

Receive_MI : Receive Masked Interrupt
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

Transmit_MI : Transmit Masked Interrupt
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RT_MI : Receive Ttimeout Masked Interrupt
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FE_MI : Framing Error Masked Interrupt
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PF_MI : Parity Error Masked Interrupt
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BE_MI : Break Error Masked Interrupt
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OE_MI : Overrun Error Masked Interrupt
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


UARTICR

UART0 Int Clear Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UARTICR UARTICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_nUARTRI_IM C_nUARTCTS_IM C_nUARTDCD_IM C_nUARTDSR_IM C_Receive_IM C_Transmit_IM C_RT_IM C_FE_IM C_PF_IM C_BE_IM C_OE_IM

C_nUARTRI_IM : Clear nUARTRI Modem Interrupt mask
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_nUARTCTS_IM : Clear nUARTCTS Modem Interrupt mask
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_nUARTDCD_IM : Clear nUARTDCD Modem Interrupt mask
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_nUARTDSR_IM : Clear nUARTDSR Modem Interrupt mask
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_Receive_IM : Clear Receive Interrupt Mask
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_Transmit_IM : Clear Transmit Interrupt Mask
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_RT_IM : Clear Receive Ttimeout Interrupt Mask
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_FE_IM : Clear Framing Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_PF_IM : Clear Parity Error Interrupt Mask
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_BE_IM : Clear Break Error Interrupt Mask
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

C_OE_IM : Clear Overrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.


UARTDMACR

UART0 DMA Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTDMACR UARTDMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxFIFO_en TxFIFO_en DMA_error

RxFIFO_en : nUARTRI Modem Interrupt mask
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TxFIFO_en : nUARTCTS Modem Interrupt mask
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_error : nUARTDCD Modem Interrupt mask
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.