\n

TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

TIM_CR1

TIM_SR

TIM_EGR

TIM_CCMR1

TIM_CCMR1_CAP

TIM_CCMR2

TIM_CCMR2_CAP

TIM_CCER

TIM_CNT

TIM_PSC

TIM_ARR

TIM_RCR

TIM_CCR1

TIM_CCR2

TIM_CCR3

TIM_CR2

TIM_CCR4

TIM_BDTR

TIM_DTG1

TIM_ISR

TIM_SMCR

TIM_DIER


TIM_CR1

Time Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CR1 TIM_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM DIR CMS ARPE CKD

CEN : Counter enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UDIS : Update disable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

URS : Update request source
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPM : One pulse mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIR : counter Direction
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMS : Center-aligned mode selection
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CKD : Clock division
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_SR

TIME status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_SR TIM_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF CC3IF CC4IF COMIF TIF BIF CC1OF CC2OF CC3OF CC4OF

UIF : Update interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1IF : Capture/Compare 1 interrupt flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2IF : Capture/Compare 2 interrupt flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3IF : Capture/Compare 3 interrupt flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4IF : Capture/Compare 4 interrupt flag
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMIF : COM interrupt flag
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIF : Break interrupt flag
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1OF : Capture/Compare 1 overcapture flag
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2OF : Capture/Compare 2 overcapture flag
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3OF : Capture/Compare 3 overcapture flag
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4OF : Capture/Compare 4 overcapture flag
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_EGR

Time event generate Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_EGR TIM_EGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G CC3G CC4G COMG TG BG

UG : Update generation
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1G : Capture/Compare 1 generation
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2G : Capture/Compare 2 generation
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3G : Capture/Compare 3 generation
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4G : Capture/Compare 4 generation
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMG : Capture/Compare control update generation
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TG : Trigger generation
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BG : Break generation
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_CCMR1

Output compare mode TIME Catch/compare mode register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CCMR1 TIM_CCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S OC1FE OC1PE OC1M OC1CE CC2S OC2FE OC2PE OC2M OC2CE

CC1S : Output compare mode CC1S
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1FE : Output compare mode OC1FE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1PE : Output compare mode OC1PE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1M : Output compare mode OC1M
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1CE : Output compare mode OC1CE
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2S : Output compare mode CC2S
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC2FE : Output compare mode OC2FE
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC2PE : Output compare mode OC2PE
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC2M : Output compare mode OC2M
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC2CE : Output compare mode OC2CE
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_CCMR1_CAP

Input capture mode TIME Catch/compare mode register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIM_CCMR1
reset_Mask : 0x0

TIM_CCMR1_CAP TIM_CCMR1_CAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S IC1PSC IC1F CC2S IC2PSC IC2F

CC1S : input capture mode CC1S
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1PSC : input capture mode IC1PSC
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1F : input capture mode IC1F
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2S : input capture mode CC2S
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC2PSC : input capture mode IC2PSC
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC2F : input capture mode IC2F
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_CCMR2

Output compare mode TIME Catch/compare mode register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CCMR2 TIM_CCMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S OC3FE OC3PE OC3M OC3CE CC4S OC4FE OC4PE OC4M OC4CE

CC3S : Output compare mode CC3S
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC3FE : Output compare mode OC3FE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC3PE : Output compare mode OC3PE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC3M : Output compare mode OC3M
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC3CE : Output compare mode OC3CE
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4S : Output compare mode CC4S
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC4FE : Output compare mode OC4FE
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC4PE : Output compare mode OC4PE
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC4M : Output compare mode OC4M
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC4CE : Output compare mode OC4CE
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_CCMR2_CAP

Input capture mode TIME Catch/compare mode register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIM_CCMR2
reset_Mask : 0x0

TIM_CCMR2_CAP TIM_CCMR2_CAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S IC3PSC IC3F CC4S IC4PSC IC4F

CC3S : input capture mode CC3S
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC3PSC : input capture mode IC3PSC
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC3F : input capture mode IC3F
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4S : input capture mode CC4S
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC4PSC : input capture mode IC4PSC
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC4F : input capture mode IC4F
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_CCER

Time catch/compare enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CCER TIM_CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NE CC1NP CC2E CC2P CC2NE CC2NP CC3E CC3P CC3NE CC3NP CC4E CC4P

CC1E : CC1E
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1P : CC1P
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1NE : CC1NE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1NP : CC1NP
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2E : CC2E
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2P : CC2P
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2NE : CC2NE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2NP : CC2NP
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3E : CC3E
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3P : CC3P
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3NE : CC3NE
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3NP : CC3NP
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4E : CC4E
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4P : CC4P
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_CNT

TIMe_CNT register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIM_CNT TIM_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_PSC

TIM1_PSC register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_PSC TIM_PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_ARR

TIM1_ARR register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_ARR TIM_ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_RCR

TIM1_RCR register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_RCR TIM_RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_CCR1

TIM1_CCR1 register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CCR1 TIM_CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_CCR2

TIM1_CCR2 register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CCR2 TIM_CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_CCR3

TIM1_CCR3 register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CCR3 TIM_CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_CR2

Time control2 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CR2 TIM_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCPC CCUS MMS TI1S OIS1 OIS1N OIS2 OIS2N OIS3 OIS3N OIS4

CCPC : catch/compare preloaded control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCUS : catch/compare control update selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MMS : Master mode selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TI1S : TI1 selection
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS1 : Output Idle state 1
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS1N : Output Idle state 1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS2 : Output Idle state 2
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS2N : Output Idle state 2
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS3 : Output Idle state 3
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS3N : Output Idle state 3
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS4 : Output Idle state 4
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_CCR4

TIM1_CCR4 register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_CCR4 TIM_CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_BDTR

TIM1_BDTR Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_BDTR TIM_BDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTG OSSI OSSR BKE BKP AOE MOE

DTG : Dead-time generator setup
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSSI : OSSI
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSSR : OSSR
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKE : Break enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKP : Break polarity
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOE : Automatic output enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MOE : Main output enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_DTG1

TIM1_DTG1
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_DTG1 TIM_DTG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM_ISR

TIM1_ISR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_ISR TIM_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Debug_mode Ch1_sel Ch2_sel Ch3_sel Ch4_sel Brk_sel Trc_sel

Debug_mode : Debug_mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Ch1_sel : Ch1_sel
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Ch2_sel : Ch2_sel
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Ch3_sel : Ch3_sel
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Ch4_sel : Ch4_sel
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Brk_sel : Brk_sel
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Trc_sel : Trc_sel
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_SMCR

Time slave mode control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_SMCR TIM_SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS ETF ETPS ECE ETP

SMS : Slave mode selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TS : Trigger selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ETF : External trigger filter
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ETPS : External trigger prescaler
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ECE : External clock enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ETP : External trigger polarity
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TIM_DIER

Time int enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM_DIER TIM_DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE CC3IE CC4IE COMIE TIE BIE

UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1IE : CC1IE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2IE : CC2IE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC3IE : CC3IE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC4IE : CC4IE
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMIE : COMIE
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIE : TIE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIE : BIE
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.



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