\n

DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD00 byte (0x0)
mem_usage : registers
protection :

Registers

CFG

CTRL0

CTRL1

CTRL2

CTRL3

CTRL4

CTRL5

BASE_PTR

ALT_BASE_PTR

SW_REQ

STATUS

VERSION

REQUEST_ON

ACTIVE

DONE

CFG_ERR

BUS_ERR


CFG

DMA Configure Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PORT RESET

ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORT : DMA Transmit Size
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET : DMA Transmit Size
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CTRL0

DMA Channel 0 Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PRI_ALT USE_BURST PRIORITY REQ0_SEL REQ0_MASK REQ1_SEL REQ1_MASK BUSERR_INTREN CFGERR_INTREN DMADONE_INTREN

ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CTRL1

DMA Channel 1 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PRI_ALT USE_BURST PRIORITY REQ0_SEL REQ0_MASK REQ1_SEL REQ1_MASK BUSERR_INTREN CFGERR_INTREN DMADONE_INTREN

ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CTRL2

DMA Channel 2 Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PRI_ALT USE_BURST PRIORITY REQ0_SEL REQ0_MASK REQ1_SEL REQ1_MASK BUSERR_INTREN CFGERR_INTREN DMADONE_INTREN

ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CTRL3

DMA Channel 3 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PRI_ALT USE_BURST PRIORITY REQ0_SEL REQ0_MASK REQ1_SEL REQ1_MASK BUSERR_INTREN CFGERR_INTREN DMADONE_INTREN

ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CTRL4

DMA Channel 4 Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL4 CTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PRI_ALT USE_BURST PRIORITY REQ0_SEL REQ0_MASK REQ1_SEL REQ1_MASK BUSERR_INTREN CFGERR_INTREN DMADONE_INTREN

ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CTRL5

DMA Channel 5 Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL5 CTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PRI_ALT USE_BURST PRIORITY REQ0_SEL REQ0_MASK REQ1_SEL REQ1_MASK BUSERR_INTREN CFGERR_INTREN DMADONE_INTREN

ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


BASE_PTR

Channel Control Base Address Pointer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE_PTR BASE_PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ALT_BASE_PTR

Channel Standby Control Base Address Pointer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ALT_BASE_PTR ALT_BASE_PTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SW_REQ

Software Request Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SW_REQ SW_REQ write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQ0 REQ1 REQ2 REQ3 REQ4 REQ5

REQ0 : DMA SW REQ0
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQ1 : DMA SW REQ1
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQ2 : DMA SW REQ2
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQ3 : DMA SW REQ3
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQ4 : DMA SW REQ4
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQ5 : DMA SW REQ5
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.


STATUS

DMA Status Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE STATE CREQ_NUM_MINUS1 CHNL_NUM_MINUS1

ENABLE : Package Size
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STATE : Transmit Size
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CREQ_NUM_MINUS1 : Busy
bits : 8 - 12 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CHNL_NUM_MINUS1 : Busy
bits : 16 - 20 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.


VERSION

DMA Version Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

REQUEST_ON

DMA Request Wait Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REQUEST_ON REQUEST_ON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ON0 ON1 ON2 ON3 ON4 ON5

ON0 : DMA REQUEST ON0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ON1 : DMA REQUEST ON1
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ON2 : DMA REQUEST ON2
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ON3 : DMA REQUEST ON3
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ON4 : DMA REQUEST ON4
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ON5 : DMA REQUEST ON5
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


ACTIVE

Active Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACTIVE ACTIVE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5

ACTIVE0 : DMA ACTIVE0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTIVE1 : DMA ACTIVE1
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTIVE2 : DMA ACTIVE2
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTIVE3 : DMA ACTIVE3
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTIVE4 : DMA ACTIVE4
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTIVE5 : DMA ACTIVE5
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


DONE

Done Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DONE DONE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE0 DONE1 DONE2 DONE3 DONE4 DONE5

DONE0 : DMA DONE0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DONE1 : DMA DONE1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DONE2 : DMA DONE2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DONE3 : DMA DONE3
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DONE4 : DMA DONE4
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DONE5 : DMA DONE5
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CFG_ERR

Configure Error Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG_ERR CFG_ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR0 ERR1 ERR2 ERR3 ERR4 ERR5

ERR0 : DMA CFG ERR0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR1 : DMA CFG ERR1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR2 : DMA CFG ERR2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR3 : DMA CFG ERR3
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR4 : DMA CFG ERR4
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR5 : DMA CFG ERR5
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


BUS_ERR

Bus Error Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS_ERR BUS_ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR0 ERR1 ERR2 ERR3 ERR4 ERR5

ERR0 : DMA BUS ERR0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR1 : DMA BUS ERR1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR2 : DMA BUS ERR2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR3 : DMA BUS ERR3
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR4 : DMA BUS ERR4
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERR5 : DMA BUS ERR5
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.



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