\n
address_offset : 0x0 Bytes (0x0)
size : 0xD00 byte (0x0)
mem_usage : registers
protection :
DMA Configure Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PORT : DMA Transmit Size
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
RESET : DMA Transmit Size
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMA Channel 0 Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMA Channel 1 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMA Channel 2 Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMA Channel 3 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMA Channel 4 Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMA Channel 5 Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA Transmit Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRI_ALT : DMA Transmit Size
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
USE_BURST : DMA Transmit Size
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
PRIORITY : DMA Transmit Size
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_SEL : DMA Transmit Size
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ0_MASK : DMA Transmit Size
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_SEL : DMA Transmit Size
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
REQ1_MASK : DMA Transmit Size
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
BUSERR_INTREN : DMA Transmit Size
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CFGERR_INTREN : DMA Transmit Size
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DMADONE_INTREN : DMA Transmit Size
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Channel Control Base Address Pointer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Channel Standby Control Base Address Pointer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Software Request Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
REQ0 : DMA SW REQ0
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
REQ1 : DMA SW REQ1
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
REQ2 : DMA SW REQ2
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
REQ3 : DMA SW REQ3
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
REQ4 : DMA SW REQ4
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
REQ5 : DMA SW REQ5
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
End of enumeration elements list.
DMA Status Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Package Size
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
STATE : Transmit Size
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
End of enumeration elements list.
CREQ_NUM_MINUS1 : Busy
bits : 8 - 12 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
CHNL_NUM_MINUS1 : Busy
bits : 16 - 20 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
DMA Version Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA Request Wait Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ON0 : DMA REQUEST ON0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ON1 : DMA REQUEST ON1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ON2 : DMA REQUEST ON2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ON3 : DMA REQUEST ON3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ON4 : DMA REQUEST ON4
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ON5 : DMA REQUEST ON5
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Active Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : DMA ACTIVE0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ACTIVE1 : DMA ACTIVE1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ACTIVE2 : DMA ACTIVE2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ACTIVE3 : DMA ACTIVE3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ACTIVE4 : DMA ACTIVE4
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ACTIVE5 : DMA ACTIVE5
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Done Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE0 : DMA DONE0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DONE1 : DMA DONE1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DONE2 : DMA DONE2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DONE3 : DMA DONE3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DONE4 : DMA DONE4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
DONE5 : DMA DONE5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Configure Error Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR0 : DMA CFG ERR0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR1 : DMA CFG ERR1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR2 : DMA CFG ERR2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR3 : DMA CFG ERR3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR4 : DMA CFG ERR4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR5 : DMA CFG ERR5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Bus Error Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR0 : DMA BUS ERR0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR1 : DMA BUS ERR1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR2 : DMA BUS ERR2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR3 : DMA BUS ERR3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR4 : DMA BUS ERR4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ERR5 : DMA BUS ERR5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
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