\n

CACHE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

MAIN_CTRL

HIT_LO

HIT_HI

MISS_LO

MULT_MISS_HI

INTR

SOFTRESET

CTRL

OPADDR

OPSIZE


MAIN_CTRL

Main Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAIN_CTRL MAIN_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHE_EN CACHE_RAM_EN

CACHE_EN : CACHE Enable
bits : 0 - 0 (1 bit)
access : read-write

CACHE_RAM_EN : CACHE used as ram
bits : 8 - 8 (1 bit)
access : read-write


HIT_LO

CACHE hit number low register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HIT_LO HIT_LO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HIT_HI

CACHE hit number high register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HIT_HI HIT_HI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MISS_LO

CACHE miss number low register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MISS_LO MISS_LO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MULT_MISS_HI

CACHE miss number high register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MULT_MISS_HI MULT_MISS_HI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INTR

CACHE interrupt register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATE_ERR TAGRAM_PARITY_ERR DATARAM_PARITY_ERR STATISTICS_ERR STATE_ERR_INTEN TAGRAM_PARITY_ERR_INTEN DATARAM_PARITY_ERR_INTEN STATISTICS_ERR_INTEN

STATE_ERR : CACHE state error status
bits : 1 - 1 (1 bit)
access : read-write

TAGRAM_PARITY_ERR : TAGRAM parity error status
bits : 2 - 2 (1 bit)
access : read-write

DATARAM_PARITY_ERR : DATARAM parity error status
bits : 3 - 3 (1 bit)
access : read-write

STATISTICS_ERR : CACHE statistics error status
bits : 5 - 5 (1 bit)
access : read-write

STATE_ERR_INTEN : CACHE state error interrupt enable
bits : 17 - 17 (1 bit)
access : read-write

TAGRAM_PARITY_ERR_INTEN : TAGRAM parity error interrupt enable
bits : 18 - 18 (1 bit)
access : read-write

DATARAM_PARITY_ERR_INTEN : DATARAM parity error interrupt enable
bits : 19 - 19 (1 bit)
access : read-write

STATISTICS_ERR_INTEN : CACHE statistics error interrupt enable
bits : 21 - 21 (1 bit)
access : read-write


SOFTRESET

CACHE software reset register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOFTRESET SOFTRESET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTRL

CACHE Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOFILL AUTOFILLING AUTOFILL_END LOADLOCK RUNLOCK AUTOCLEAR AUTOCLEARING AUTOCLEAR_END UNLOCK UNLOCKING UNLOCK_END UNVALID STATISTICS_EN

AUTOFILL : CACHE autofill trig
bits : 0 - 0 (1 bit)
access : read-write

AUTOFILLING : CACHE is autofilling
bits : 1 - 1 (1 bit)
access : read-only

AUTOFILL_END : CACHE autofill end flag
bits : 2 - 2 (1 bit)
access : read-write

LOADLOCK : CACHE lock control
bits : 4 - 4 (1 bit)
access : read-write

RUNLOCK : CACHE runlock control
bits : 5 - 5 (1 bit)
access : read-write

AUTOCLEAR : CACHE autoclear trig
bits : 8 - 8 (1 bit)
access : read-write

AUTOCLEARING : CACHE is autoclearing
bits : 9 - 9 (1 bit)
access : read-only

AUTOCLEAR_END : CACHE autoclear end flag
bits : 10 - 10 (1 bit)
access : read-write

UNLOCK : CACHE unlock control
bits : 16 - 16 (1 bit)
access : read-write

UNLOCKING : CACHE is unlocking
bits : 17 - 17 (1 bit)
access : read-only

UNLOCK_END : CACHE unlock end flag
bits : 18 - 18 (1 bit)
access : read-write

UNVALID : CACHE unvalid control
bits : 20 - 20 (1 bit)
access : read-write

STATISTICS_EN : CACHE statistics enable
bits : 30 - 30 (1 bit)
access : read-write


OPADDR

CACHE lock start address
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPADDR OPADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : CACHE lock start address
bits : 0 - 17 (18 bit)
access : read-write


OPSIZE

CACHE lock line size
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPSIZE OPSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINE_SIZE

LINE_SIZE : CACHE lock line size
bits : 0 - 7 (8 bit)
access : read-write



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