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SYSREG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

PWM_CFG

INTR_STATUS0

INTR_STATUS1

CHIP_ID

PREFETCH_BYPASS_BUFFER_HIT_CNT

PREFETCH_CACHE_HIT_CNT

PREFETCH_DATA_BUFFER_HIT_CNT

PREFETCH_INST_BUFFER_HIT_CNT

ETIMER_CFG

PREFETCH_STATE

SYSTICK_CFG

CPU1_ADDR0_REMAP_CFG

CPU1_ADDR4_REMAP_CFG

PREFETCH_CFG

PREFETCH_BYPASS_CFG

SYSRAM_CTRL

RXEV_CTRL

ACCESS_EN

MISC_CTRL

VERSION


PWM_CFG

PWM confige Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CFG PWM_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0_SYNC PWM1_SYNC PWM2_SYNC PWM3_SYNC PWM4_SYNC PWM5_SYNC PWM6_SYNC PWM7_SYNC PWM_TZ3_CPSEL PWM_TZ5_FSEL PWM_FRC_STOP

PWM0_SYNC : PWM0 synchronous
bits : 0 - 0 (1 bit)
access : read-write

PWM1_SYNC : PWM1 synchronous
bits : 1 - 1 (1 bit)
access : read-write

PWM2_SYNC : PWM2 synchronous
bits : 2 - 2 (1 bit)
access : read-write

PWM3_SYNC : PWM3 synchronous
bits : 3 - 3 (1 bit)
access : read-write

PWM4_SYNC : PWM4 synchronous
bits : 4 - 4 (1 bit)
access : read-write

PWM5_SYNC : PWM5 synchronous
bits : 5 - 5 (1 bit)
access : read-write

PWM6_SYNC : PWM6 synchronous
bits : 6 - 6 (1 bit)
access : read-write

PWM7_SYNC : PWM7 synchronous
bits : 7 - 7 (1 bit)
access : read-write

PWM_TZ3_CPSEL : PWM TZ3 select
bits : 16 - 17 (2 bit)
access : read-write

PWM_TZ5_FSEL : PWM TZ5 select
bits : 20 - 20 (1 bit)
access : read-write

PWM_FRC_STOP : PWM force stop
bits : 23 - 23 (1 bit)
access : read-write


INTR_STATUS0

interrupt status register 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTR_STATUS0 INTR_STATUS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART1_INTR UART2_INTR SSP0_INTR SSP1_INTR SSP2_INTR SSP3_INTR I2C_INTR GPIO_GP0_INTR GPIO_GP1_INTR GPIO_GP2_INTR GPIO_GP3_INTR GPIO_GP4_INTR GPIO_GP5_INTR PWM0_INTR PWM1_INTR PWM2_INTR PWM3_INTR PWM4_INTR PWM5_INTR PWM6_INTR PWM7_INTR

UART1_INTR : UART1 interrupt status
bits : 0 - 0 (1 bit)
access : read-only

UART2_INTR : UART2 interrupt status
bits : 1 - 1 (1 bit)
access : read-only

SSP0_INTR : SSP0 interrupt status
bits : 2 - 2 (1 bit)
access : read-only

SSP1_INTR : SSP1 interrupt status
bits : 3 - 3 (1 bit)
access : read-only

SSP2_INTR : SSP2 interrupt status
bits : 4 - 4 (1 bit)
access : read-only

SSP3_INTR : SSP3 interrupt status
bits : 5 - 5 (1 bit)
access : read-only

I2C_INTR : I2C interrupt status
bits : 6 - 6 (1 bit)
access : read-only

GPIO_GP0_INTR : GPIO0 interrupt status
bits : 7 - 7 (1 bit)
access : read-only

GPIO_GP1_INTR : GPIO1 interrupt status
bits : 8 - 8 (1 bit)
access : read-only

GPIO_GP2_INTR : GPIO2 interrupt status
bits : 9 - 9 (1 bit)
access : read-only

GPIO_GP3_INTR : GPIO3 interrupt status
bits : 10 - 10 (1 bit)
access : read-only

GPIO_GP4_INTR : GPIO4 interrupt status
bits : 11 - 11 (1 bit)
access : read-only

GPIO_GP5_INTR : GPIO5 interrupt status
bits : 12 - 12 (1 bit)
access : read-only

PWM0_INTR : PWM0 interrupt status
bits : 16 - 16 (1 bit)
access : read-only

PWM1_INTR : PWM1 interrupt status
bits : 17 - 17 (1 bit)
access : read-only

PWM2_INTR : PWM2 interrupt status
bits : 18 - 18 (1 bit)
access : read-only

PWM3_INTR : PWM3 interrupt status
bits : 19 - 19 (1 bit)
access : read-only

PWM4_INTR : PWM4 interrupt status
bits : 20 - 20 (1 bit)
access : read-only

PWM5_INTR : PWM5 interrupt status
bits : 21 - 21 (1 bit)
access : read-only

PWM6_INTR : PWM6 interrupt status
bits : 22 - 22 (1 bit)
access : read-only

PWM7_INTR : PWM7 interrupt status
bits : 23 - 23 (1 bit)
access : read-only


INTR_STATUS1

interrupt status register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTR_STATUS1 INTR_STATUS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0_TZ_INTR PWM1_TZ_INTR PWM2_TZ_INTR PWM3_TZ_INTR PWM4_TZ_INTR PWM5_TZ_INTR PWM6_TZ_INTR PWM7_TZ_INTR WDT0_INTR WDT1_INTR SYSRAM0_PARITY_INTR SYSRAM1_PARITY_INTR ATOM_INTR PPU_INTR EFLASH_INTR DIV_BY_0_INTR MAC_OV_INTR CORDIC_INTR SND_MAC_OV_INTR

PWM0_TZ_INTR : PWM0 TZ interrupt status
bits : 0 - 0 (1 bit)
access : read-only

PWM1_TZ_INTR : PWM1 TZ interrupt status
bits : 1 - 1 (1 bit)
access : read-only

PWM2_TZ_INTR : PWM2 TZ interrupt status
bits : 2 - 2 (1 bit)
access : read-only

PWM3_TZ_INTR : PWM3 TZ interrupt status
bits : 3 - 3 (1 bit)
access : read-only

PWM4_TZ_INTR : PWM4 TZ interrupt status
bits : 4 - 4 (1 bit)
access : read-only

PWM5_TZ_INTR : PWM5 TZ interrupt status
bits : 5 - 5 (1 bit)
access : read-only

PWM6_TZ_INTR : PWM6 TZ interrupt status
bits : 6 - 6 (1 bit)
access : read-only

PWM7_TZ_INTR : PWM7 TZ interrupt status
bits : 7 - 7 (1 bit)
access : read-only

WDT0_INTR : WDT0 interrupt status
bits : 8 - 8 (1 bit)
access : read-only

WDT1_INTR : WDT1 interrupt status
bits : 9 - 9 (1 bit)
access : read-only

SYSRAM0_PARITY_INTR : sysram0 parity interrupt status
bits : 10 - 10 (1 bit)
access : read-only

SYSRAM1_PARITY_INTR : sysram1 parity interrupt status
bits : 11 - 11 (1 bit)
access : read-only

ATOM_INTR : atom interrupt status
bits : 16 - 16 (1 bit)
access : read-only

PPU_INTR : ppu interrupt status
bits : 17 - 17 (1 bit)
access : read-only

EFLASH_INTR : eflash interrupt status
bits : 18 - 18 (1 bit)
access : read-only

DIV_BY_0_INTR : divide by 0 interrupt status
bits : 25 - 25 (1 bit)
access : read-only

MAC_OV_INTR : mac overflow interrupt status
bits : 26 - 26 (1 bit)
access : read-only

CORDIC_INTR : cordic interrupt status
bits : 27 - 27 (1 bit)
access : read-only

SND_MAC_OV_INTR : second mac overflow interrupt status
bits : 28 - 28 (1 bit)
access : read-only


CHIP_ID

CHIP_ID Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID CHIP_ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PREFETCH_BYPASS_BUFFER_HIT_CNT

Prefetch Bypass Buffer Hit Counter Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_BYPASS_BUFFER_HIT_CNT PREFETCH_BYPASS_BUFFER_HIT_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PREFETCH_CACHE_HIT_CNT

Prefetch Cache Hit Counter Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_CACHE_HIT_CNT PREFETCH_CACHE_HIT_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PREFETCH_DATA_BUFFER_HIT_CNT

Prefetch Data Buffer Hit Counter Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_DATA_BUFFER_HIT_CNT PREFETCH_DATA_BUFFER_HIT_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PREFETCH_INST_BUFFER_HIT_CNT

Prefetch Instruction Hit Counter Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_INST_BUFFER_HIT_CNT PREFETCH_INST_BUFFER_HIT_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETIMER_CFG

ETIMER confige Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETIMER_CFG ETIMER_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PREFETCH_STATE

Prefetch State Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_STATE PREFETCH_STATE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREFETCH_STATE

PREFETCH_STATE : Prefetch State
bits : 0 - 2 (3 bit)
access : read-only


SYSTICK_CFG

SYSTICK confige Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSTICK_CFG SYSTICK_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCALIB SKEW NOREF

STCALIB : clock calibration value
bits : 0 - 23 (24 bit)
access : read-write

SKEW : clock skew
bits : 24 - 24 (1 bit)
access : read-write

NOREF : clock reference select
bits : 25 - 25 (1 bit)
access : read-write


CPU1_ADDR0_REMAP_CFG

CPU1 Address0 Remap Confige Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU1_ADDR0_REMAP_CFG CPU1_ADDR0_REMAP_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CPU1_ADDR4_REMAP_CFG

CPU1 Address4 Remap Confige Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU1_ADDR4_REMAP_CFG CPU1_ADDR4_REMAP_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PREFETCH_CFG

Prefetch Confige Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_CFG PREFETCH_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREFETCH_EN ONLY_CACHE ONLY_BUF0 ONLY_BUF1 PREFETCH_INFO_RST CPU1_REMAP_EN

PREFETCH_EN : Prefetch Enable
bits : 0 - 0 (1 bit)
access : read-write

ONLY_CACHE : Cache Used Only
bits : 1 - 1 (1 bit)
access : read-write

ONLY_BUF0 : CPU0 Used Buffer Only
bits : 2 - 2 (1 bit)
access : read-write

ONLY_BUF1 : CPU1 Used Buffer Only
bits : 3 - 3 (1 bit)
access : read-write

PREFETCH_INFO_RST : Prefetch Info Reset
bits : 4 - 4 (1 bit)
access : read-write

CPU1_REMAP_EN : CPU1 Remap Enable
bits : 8 - 8 (1 bit)
access : read-write


PREFETCH_BYPASS_CFG

Prefetch Bypass Confige Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREFETCH_BYPASS_CFG PREFETCH_BYPASS_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_ADDR

BYPASS_ADDR : Prefetch Bypass Address
bits : 0 - 18 (19 bit)
access : read-write


SYSRAM_CTRL

RAM control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSRAM_CTRL SYSRAM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sysram0_parity_intren sysram0_parity_err_clr sysram1_parity_intren sysram1_parity_err_clr sysram0_ms sysram0_mse sysram1_ms sysram1_mse

sysram0_parity_intren : System RAM0 parity error interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

sysram0_parity_err_clr : System RAM0 parity error cleanup
bits : 9 - 9 (1 bit)
access : read-write

sysram1_parity_intren : System RAM1 parity error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

sysram1_parity_err_clr : System RAM1 parity error cleanup
bits : 11 - 11 (1 bit)
access : read-write

sysram0_ms : System RAM0 M31 reserved
bits : 16 - 19 (4 bit)
access : read-write

sysram0_mse : System RAM0 M31 reserved
bits : 23 - 23 (1 bit)
access : read-write

sysram1_ms : System RAM1 M31 reserved
bits : 24 - 27 (4 bit)
access : read-write

sysram1_mse : System RAM1 M31 reserved
bits : 31 - 31 (1 bit)
access : read-write


RXEV_CTRL

RXEV control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXEV_CTRL RXEV_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA IWDT CHIPCTRL GPIO0 GPIO1 GPIO2 ERU0 ERU1 ERU2 ERU3 RXEV_EN DMA_C1 IWDT_C1 CHIPCTRL_C1 GPIO0_C1 GPIO1_C1 GPIO2_C1 ERU0_C1 ERU1_C1 ERU2_C1 ERU3_C1 RXEV_EN_C1

DMA : DMA intterupt connect enable
bits : 0 - 0 (1 bit)
access : read-write

IWDT : IWDT intterupt connect enable
bits : 1 - 1 (1 bit)
access : read-write

CHIPCTRL : CHIPCTRL intterupt connect enable
bits : 2 - 2 (1 bit)
access : read-write

GPIO0 : GPIO0 intterupt connect enable
bits : 3 - 3 (1 bit)
access : read-write

GPIO1 : GPIO1 intterupt connect enable
bits : 4 - 4 (1 bit)
access : read-write

GPIO2 : GPIO2 intterupt connect enable
bits : 5 - 5 (1 bit)
access : read-write

ERU0 : ERU0 intterupt connect enable
bits : 6 - 6 (1 bit)
access : read-write

ERU1 : ERU1 intterupt connect enable
bits : 7 - 7 (1 bit)
access : read-write

ERU2 : ERU2 intterupt connect enable
bits : 8 - 8 (1 bit)
access : read-write

ERU3 : ERU3 intterupt connect enable
bits : 9 - 9 (1 bit)
access : read-write

RXEV_EN : RVEV enable
bits : 15 - 15 (1 bit)
access : read-write

DMA_C1 : DMA intterupt connect enable for core 1
bits : 16 - 16 (1 bit)
access : read-write

IWDT_C1 : IWDT intterupt connect enable for core 1
bits : 17 - 17 (1 bit)
access : read-write

CHIPCTRL_C1 : CHIPCTRL intterupt connect enable for core 1
bits : 18 - 18 (1 bit)
access : read-write

GPIO0_C1 : GPIO0 intterupt connect enable for core 1
bits : 19 - 19 (1 bit)
access : read-write

GPIO1_C1 : GPIO1 intterupt connect enable for core 1
bits : 20 - 20 (1 bit)
access : read-write

GPIO2_C1 : GPIO2 intterupt connect enable for core 1
bits : 21 - 21 (1 bit)
access : read-write

ERU0_C1 : ERU0 intterupt connect enable for core 1
bits : 22 - 22 (1 bit)
access : read-write

ERU1_C1 : ERU1 intterupt connect enable for core 1
bits : 23 - 23 (1 bit)
access : read-write

ERU2_C1 : ERU2 intterupt connect enable for core 1
bits : 24 - 24 (1 bit)
access : read-write

ERU3_C1 : ERU3 intterupt connect enable for core 1
bits : 25 - 25 (1 bit)
access : read-write

RXEV_EN_C1 : RVEV enable for core 1
bits : 31 - 31 (1 bit)
access : read-write


ACCESS_EN

ACCESS ENABLE Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACCESS_EN ACCESS_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MISC_CTRL

MISC control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CTRL MISC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0_OUTEN UART2_OUTEN

UART0_OUTEN : UART0 output enable in half-duplex mode
bits : 0 - 0 (1 bit)
access : read-write

UART2_OUTEN : UART2 output enable in half-duplex mode
bits : 2 - 2 (1 bit)
access : read-write


VERSION

VERSION Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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