\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
PWM confige Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0_SYNC : PWM0 synchronous
bits : 0 - 0 (1 bit)
access : read-write
PWM1_SYNC : PWM1 synchronous
bits : 1 - 1 (1 bit)
access : read-write
PWM2_SYNC : PWM2 synchronous
bits : 2 - 2 (1 bit)
access : read-write
PWM3_SYNC : PWM3 synchronous
bits : 3 - 3 (1 bit)
access : read-write
PWM4_SYNC : PWM4 synchronous
bits : 4 - 4 (1 bit)
access : read-write
PWM5_SYNC : PWM5 synchronous
bits : 5 - 5 (1 bit)
access : read-write
PWM6_SYNC : PWM6 synchronous
bits : 6 - 6 (1 bit)
access : read-write
PWM7_SYNC : PWM7 synchronous
bits : 7 - 7 (1 bit)
access : read-write
PWM_TZ3_CPSEL : PWM TZ3 select
bits : 16 - 17 (2 bit)
access : read-write
PWM_TZ5_FSEL : PWM TZ5 select
bits : 20 - 20 (1 bit)
access : read-write
PWM_FRC_STOP : PWM force stop
bits : 23 - 23 (1 bit)
access : read-write
interrupt status register 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UART1_INTR : UART1 interrupt status
bits : 0 - 0 (1 bit)
access : read-only
UART2_INTR : UART2 interrupt status
bits : 1 - 1 (1 bit)
access : read-only
SSP0_INTR : SSP0 interrupt status
bits : 2 - 2 (1 bit)
access : read-only
SSP1_INTR : SSP1 interrupt status
bits : 3 - 3 (1 bit)
access : read-only
SSP2_INTR : SSP2 interrupt status
bits : 4 - 4 (1 bit)
access : read-only
SSP3_INTR : SSP3 interrupt status
bits : 5 - 5 (1 bit)
access : read-only
I2C_INTR : I2C interrupt status
bits : 6 - 6 (1 bit)
access : read-only
GPIO_GP0_INTR : GPIO0 interrupt status
bits : 7 - 7 (1 bit)
access : read-only
GPIO_GP1_INTR : GPIO1 interrupt status
bits : 8 - 8 (1 bit)
access : read-only
GPIO_GP2_INTR : GPIO2 interrupt status
bits : 9 - 9 (1 bit)
access : read-only
GPIO_GP3_INTR : GPIO3 interrupt status
bits : 10 - 10 (1 bit)
access : read-only
GPIO_GP4_INTR : GPIO4 interrupt status
bits : 11 - 11 (1 bit)
access : read-only
GPIO_GP5_INTR : GPIO5 interrupt status
bits : 12 - 12 (1 bit)
access : read-only
PWM0_INTR : PWM0 interrupt status
bits : 16 - 16 (1 bit)
access : read-only
PWM1_INTR : PWM1 interrupt status
bits : 17 - 17 (1 bit)
access : read-only
PWM2_INTR : PWM2 interrupt status
bits : 18 - 18 (1 bit)
access : read-only
PWM3_INTR : PWM3 interrupt status
bits : 19 - 19 (1 bit)
access : read-only
PWM4_INTR : PWM4 interrupt status
bits : 20 - 20 (1 bit)
access : read-only
PWM5_INTR : PWM5 interrupt status
bits : 21 - 21 (1 bit)
access : read-only
PWM6_INTR : PWM6 interrupt status
bits : 22 - 22 (1 bit)
access : read-only
PWM7_INTR : PWM7 interrupt status
bits : 23 - 23 (1 bit)
access : read-only
interrupt status register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM0_TZ_INTR : PWM0 TZ interrupt status
bits : 0 - 0 (1 bit)
access : read-only
PWM1_TZ_INTR : PWM1 TZ interrupt status
bits : 1 - 1 (1 bit)
access : read-only
PWM2_TZ_INTR : PWM2 TZ interrupt status
bits : 2 - 2 (1 bit)
access : read-only
PWM3_TZ_INTR : PWM3 TZ interrupt status
bits : 3 - 3 (1 bit)
access : read-only
PWM4_TZ_INTR : PWM4 TZ interrupt status
bits : 4 - 4 (1 bit)
access : read-only
PWM5_TZ_INTR : PWM5 TZ interrupt status
bits : 5 - 5 (1 bit)
access : read-only
PWM6_TZ_INTR : PWM6 TZ interrupt status
bits : 6 - 6 (1 bit)
access : read-only
PWM7_TZ_INTR : PWM7 TZ interrupt status
bits : 7 - 7 (1 bit)
access : read-only
WDT0_INTR : WDT0 interrupt status
bits : 8 - 8 (1 bit)
access : read-only
WDT1_INTR : WDT1 interrupt status
bits : 9 - 9 (1 bit)
access : read-only
SYSRAM0_PARITY_INTR : sysram0 parity interrupt status
bits : 10 - 10 (1 bit)
access : read-only
SYSRAM1_PARITY_INTR : sysram1 parity interrupt status
bits : 11 - 11 (1 bit)
access : read-only
ATOM_INTR : atom interrupt status
bits : 16 - 16 (1 bit)
access : read-only
PPU_INTR : ppu interrupt status
bits : 17 - 17 (1 bit)
access : read-only
EFLASH_INTR : eflash interrupt status
bits : 18 - 18 (1 bit)
access : read-only
DIV_BY_0_INTR : divide by 0 interrupt status
bits : 25 - 25 (1 bit)
access : read-only
MAC_OV_INTR : mac overflow interrupt status
bits : 26 - 26 (1 bit)
access : read-only
CORDIC_INTR : cordic interrupt status
bits : 27 - 27 (1 bit)
access : read-only
SND_MAC_OV_INTR : second mac overflow interrupt status
bits : 28 - 28 (1 bit)
access : read-only
CHIP_ID Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Prefetch Bypass Buffer Hit Counter Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Prefetch Cache Hit Counter Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Prefetch Data Buffer Hit Counter Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Prefetch Instruction Hit Counter Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETIMER confige Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Prefetch State Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREFETCH_STATE : Prefetch State
bits : 0 - 2 (3 bit)
access : read-only
SYSTICK confige Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCALIB : clock calibration value
bits : 0 - 23 (24 bit)
access : read-write
SKEW : clock skew
bits : 24 - 24 (1 bit)
access : read-write
NOREF : clock reference select
bits : 25 - 25 (1 bit)
access : read-write
CPU1 Address0 Remap Confige Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU1 Address4 Remap Confige Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Prefetch Confige Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFETCH_EN : Prefetch Enable
bits : 0 - 0 (1 bit)
access : read-write
ONLY_CACHE : Cache Used Only
bits : 1 - 1 (1 bit)
access : read-write
ONLY_BUF0 : CPU0 Used Buffer Only
bits : 2 - 2 (1 bit)
access : read-write
ONLY_BUF1 : CPU1 Used Buffer Only
bits : 3 - 3 (1 bit)
access : read-write
PREFETCH_INFO_RST : Prefetch Info Reset
bits : 4 - 4 (1 bit)
access : read-write
CPU1_REMAP_EN : CPU1 Remap Enable
bits : 8 - 8 (1 bit)
access : read-write
Prefetch Bypass Confige Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_ADDR : Prefetch Bypass Address
bits : 0 - 18 (19 bit)
access : read-write
RAM control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sysram0_parity_intren : System RAM0 parity error interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
sysram0_parity_err_clr : System RAM0 parity error cleanup
bits : 9 - 9 (1 bit)
access : read-write
sysram1_parity_intren : System RAM1 parity error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
sysram1_parity_err_clr : System RAM1 parity error cleanup
bits : 11 - 11 (1 bit)
access : read-write
sysram0_ms : System RAM0 M31 reserved
bits : 16 - 19 (4 bit)
access : read-write
sysram0_mse : System RAM0 M31 reserved
bits : 23 - 23 (1 bit)
access : read-write
sysram1_ms : System RAM1 M31 reserved
bits : 24 - 27 (4 bit)
access : read-write
sysram1_mse : System RAM1 M31 reserved
bits : 31 - 31 (1 bit)
access : read-write
RXEV control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA intterupt connect enable
bits : 0 - 0 (1 bit)
access : read-write
IWDT : IWDT intterupt connect enable
bits : 1 - 1 (1 bit)
access : read-write
CHIPCTRL : CHIPCTRL intterupt connect enable
bits : 2 - 2 (1 bit)
access : read-write
GPIO0 : GPIO0 intterupt connect enable
bits : 3 - 3 (1 bit)
access : read-write
GPIO1 : GPIO1 intterupt connect enable
bits : 4 - 4 (1 bit)
access : read-write
GPIO2 : GPIO2 intterupt connect enable
bits : 5 - 5 (1 bit)
access : read-write
ERU0 : ERU0 intterupt connect enable
bits : 6 - 6 (1 bit)
access : read-write
ERU1 : ERU1 intterupt connect enable
bits : 7 - 7 (1 bit)
access : read-write
ERU2 : ERU2 intterupt connect enable
bits : 8 - 8 (1 bit)
access : read-write
ERU3 : ERU3 intterupt connect enable
bits : 9 - 9 (1 bit)
access : read-write
RXEV_EN : RVEV enable
bits : 15 - 15 (1 bit)
access : read-write
DMA_C1 : DMA intterupt connect enable for core 1
bits : 16 - 16 (1 bit)
access : read-write
IWDT_C1 : IWDT intterupt connect enable for core 1
bits : 17 - 17 (1 bit)
access : read-write
CHIPCTRL_C1 : CHIPCTRL intterupt connect enable for core 1
bits : 18 - 18 (1 bit)
access : read-write
GPIO0_C1 : GPIO0 intterupt connect enable for core 1
bits : 19 - 19 (1 bit)
access : read-write
GPIO1_C1 : GPIO1 intterupt connect enable for core 1
bits : 20 - 20 (1 bit)
access : read-write
GPIO2_C1 : GPIO2 intterupt connect enable for core 1
bits : 21 - 21 (1 bit)
access : read-write
ERU0_C1 : ERU0 intterupt connect enable for core 1
bits : 22 - 22 (1 bit)
access : read-write
ERU1_C1 : ERU1 intterupt connect enable for core 1
bits : 23 - 23 (1 bit)
access : read-write
ERU2_C1 : ERU2 intterupt connect enable for core 1
bits : 24 - 24 (1 bit)
access : read-write
ERU3_C1 : ERU3 intterupt connect enable for core 1
bits : 25 - 25 (1 bit)
access : read-write
RXEV_EN_C1 : RVEV enable for core 1
bits : 31 - 31 (1 bit)
access : read-write
ACCESS ENABLE Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0_OUTEN : UART0 output enable in half-duplex mode
bits : 0 - 0 (1 bit)
access : read-write
UART2_OUTEN : UART2 output enable in half-duplex mode
bits : 2 - 2 (1 bit)
access : read-write
VERSION Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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